Engineering Manager & Technical Leader in Platform Engineering Group - Working on Artificial Intelligence Products - Server Segment – Functional Validation – Lead Circuit Marginality Validation, managing Post-Silicon Validation of Latest Server Processors (Xeon & IPF) - Energetic leader driving products from Design to Product Release. Worked on Design, Debug, Systems-Tester correlation, Timing, Product Rejects, Test-hole resolution; interacts with Internal and external teams to ensure Customer Satisfaction. Innovation Leader who achieved High impact on Product releases, realizing Solid savings by implementing Quality and Efficiency improvements to achieve faster High Quality Product Releases. His Methodology changes, include enforcing analytic processes; Driving Emulation, Data Mining, Testing issues and other efforts to improve Product Quality and achieve faster product debug.in manufacturing, characterization and validation.- Manager & Tech. Lead of Analog Validation: improved Methodology achieving high reduction in characterization time and more reliable evaluation. Redefined DOE, improved Statistical & Analytical methods, also including data collected in other fronts.- Improved Signal Integrity methodology and team’s efficiency. Provided training and developed team’s deeper understanding and technological growth. - Sr. Processor Lead Designer at Intel-Texas - Responsible for CSI (QPI) & PCI-Express - Cluster Implementation, Functional Units, Macros & Block definition, including Embedded Building Blocks, Register Files, Data Path and I/F to Electrical Layer - Logic implementation, connectivity & floor planning. Feasibility studies, Placement, Routing, Timing analysis, Critical Paths characterization. Logic & Circuit Simulation

Lecturer of Digital Integrated Circuit Design-Student Advisor

Staff Engineer Hardware Technical Lead – Processor Design 3/1998- 6/2007Lead roles in Development of Single & Multi-core Sparc III/IV processors: Cheetah / Panther / Jaguar families & Multi-core Multi-thread processor: Rock. Including design of:- I/O Design, fast interfaces. Special IO, DFT & Process-Monitor Circuits - ESD Structures for all I/O types - Temperature Sensors & control interfaces.- Clock Distribution. Developed Optimization Technique for Higher Op. Frequency w/ min. skew - Megacells, SRAM & Register Files. RTL, Formal Verification, Spice characterization, timing analysis, noise, signal integrity, electro-migration, and layout verification.

Lead role in I/F device customization- ASICs for fast Processor / Memory data interchange (up to 1.6 Gbits/sec.)- Design retargeting for fabrication at foundries with different processes & System Integration.

New Products Division. -CAD Engineer IV – Design & Tools - Designed Mixed Signal Devices (Analog / Digital) for Temperature Measurement & Control.- Circuit & cell characterization (Bi-CMOS processes). Developed designs for tools & process mapping tests.- Installed & maintained Commercial & ADI proprietary software Application Tools