Graduate from San Jose State University in Electrical engineering (VlSI) with concentration in Analog/RF IC design/testing.Authorized to work in USA.To start career as a analog IC design/test engineer and learn things and grow with the company.Specialties: Analog/Digital/RF design projects in Cadence. CMOS circuit design in Cadence Virtuoso schematic editor. Layout done in Vrituoso layout editor. Academic project in Verilog and VHDL as well. PERL.Masters project- "Design of a 0.85V on-chip analog front-end for Ultrasound image sensing in 45nm CMOS Process technology".Presented a national level paper in "National Conference on Recent Trends in Optoelectronics and Laser Technology" NCOL-07, April 9- 11, 2007 at Kerala University, Kerala, India.