FPGA implementation of digital beam forming, phase alignment, ADC control and other features required for digital radio frequency reception and analysis.

Design FPGA code and base level software for Media over IP products. Media includes SMPTE 2022-5,6,&7 standards carried by RTP and HBRMT packages to be sent as IP packages. Design include media information error detection (missing or misplaced TRS headers, bad CRC or checksum for video and audio, freeze frame video etc). Media error correction.Test media generation via FPGA. Including test pattern of 2022-6 standard videos patterns with associated test audio of programmable frequency. Test media is then made into IP packages to be send over network.

Demodulated 802.11ac signals from raw I/Q data to produce router information.Demodulated NTSC color TV signals from raw I/Q data to produce color image in Windows environment.Software / Firmware design for xilinx microblaze related environment.

• Designed, verified, and tested PID loops driven servo control. Designs include feedback conditioning, IIR filter, PWM generation, and other peripherals that complete the standalone FPGA based servo amplifier implementation.• Designed high speed network interfaces (including EtherCAT, SyncNet, Ethernet, and Powerlink) in Xilinx’s EDK environment. • Designed asynchronous-clock, multi-FPGA, timing and control systems to simplify hardware and PCB design process.• Routinely designed serial bus interfaces (EnDat, Hiperface, BISS, SPI, etc.,), digital component control interfaces (PHY, ADC, DAC, GPIO expander, etc.,), and FPGA internal structures (PLL, Data Arbiter, Cross-clock-domain interface, etc.,).• Coded in Perl, shell scrip, and C++ to aid firmware release and hardware verification process.• Refactored past FPGA designs into modular structures to produce designs with high accuracy, low maintenance cost, and short delivery cycles. Developed and maintained testing procedures to ensure the quality of the end products.• Routinely collaborated with hardware engineers during hardware debug and verification processes.• Routinely collaborated with hardware, firmware, and verification engineers to ensure successful and timely product release and delivery cycles.

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Digital Design Engineer. Integrated Circuit design with HDL language both ASIC and FPGA designs. Project involve signals processing, control loop implementation, and general hardware control and maintenance.