Technical Staff, Hw Technologist, Office Of Isg Cto
Current
Oct 2024 - Present
AeroLeads people directory · profile
Raj Menon Email & Phone Number
Technical Staff, Office of ISG CTO @ Dell Technologies
at
Dell Technologies
1 work email found
@tintri.com
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Current company
Role
Technical Staff, Office of ISG CTO @ Dell Technologies
Location
San Francisco Bay Area, United States, United States
Who is Raj Menon? Overview
A concise factual answer block for searchers comparing this professional profile.
Quick answer
Raj Menon is listed as Technical Staff, Office of ISG CTO @ Dell Technologies at Dell Technologies, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at tintri.com and a matched LinkedIn profile for Raj Menon.
Raj Menon previously worked as Technical Staff, HW Technologist, Office of ISG CTO at Dell Technologies and Director of System Engineering at Sima.Ai. Raj Menon holds Ms, Ee from University Of Pittsburgh.
Company email context
Email format at Dell Technologies
This section adds company-level context without repeating Raj Menon's masked contact details.
{first_initial}{last}@tintri.com
86% confidence
AeroLeads found 1 current-domain work email signal for Raj Menon. Compare company email patterns before reaching out.
Profile bio
About Raj Menon
An engineer with a demonstrated history of solving complex hardware, software and systems problems. A person who loves to use a background in end-to-end product development to create innovative products and solutions to solve real world problems.
Listed skills include Asic, Device Drivers, Hardware, Compilers, and 19 others.
Current workplace
Raj Menon's current company
Company context helps verify the profile and gives searchers a useful next step.
22 roles
Raj Menon work experience
A career timeline built from the work history available for this profile.
Director Of System Engineering
- Hands on Manager and Lead of a team of PCB, System, SI/PI and test/automation engineers- Responsible for all design, bringup, verification and NPI of multiple PCBs using the SiMa 2nd Generation ML/AI SoC (Bringup/DevKit, Characterization, Production Low Profile, SOM cards)- Assisted in SoC package development- Assisted customers with designing in ML/AI.
Oct 2023 - Oct 2024
Senior Principal Engineer
- Post-Silicon Validation: SoC and multiple PCBs- Assisted with LPDDR4 testing, link stability and test automation- Fixed PCB issues with SD-Card (root caused and found Linux Kernel Bug), eMMC (root caused and found FW issue), Ethernet (root caused PCB reset issue resulting in occasional link drop)
Jan 2023 - Oct 2023
Technical Lead/Manager - Compute Hw
- Technical Lead and Manager of a team responsible for ASIL-D automotive compute modules
Sep 2021 - Nov 2022
System Test Design Lead
- Test Design Lead for entire Manufacturing Test Line for multiple high volume Mac computers
Jul 2019 - Sep 2021
Apr 2019 - Jan 2020
Feb 2006 - Apr 2019
Principal Engineer
Agylstor
- System Design and Architecture for Edge Compute/Storage Appliance.- Investigate new technologies and see if/how they can be integrated into current and future products.- Assist in Board/System Bringup and Test.- Help solve HW/SW interface issues.- Python tests for incoming part validation and system qualification.
Aug 2018 - Jul 2019
Senior Staff Engineer, Platform Hardware
- HW Lead for the storage subsystem for storage appliances. - Assist in debug of platform SW issues.- SAS and SATA SSD/HDD qualification and debugging. - Develop NVMoF proof-of-concept. - Develop new system architecture and present to the Office of the CTO. - GlusterFS protyping.- Intel SPDK, DPDK, PMDK and ISA-L proof-of-concepts and benchmarking..
Feb 2017 - Jun 2018
Sw Technologist
- Team lead for Manufacturing automation for SW installation, configuration and test. - HW System architecture for Rack Scale Hyperconverged system, help develop proof of concept. - HW System Architecture for scale-able NVMoF appliance. - HW System architecture for SWIFT and NFS/CIFS gateway appliances.
May 2015 - Jan 2017
Sw Engineer
- Team lead for test software team.- Design and development of online, offline, manufacturing, RMA test SW.
Nov 2014 - May 2015
Member Of Technical Staff - Hardware Engineer/System Architecture
- System HW Design for multiple HyperConverged appliances.- SSD and HDD qualifications.- Deleloped and supported Python scripts for manufacturing team to test final products before shipment.- Help debug manufacturing and design issues.
Apr 2013 - Oct 2014
Member Of Technical Staff, Hw
- System HW Design.- Project Lead and Manager for WAN Optimization appliance.- SAS and SATA bus and protocol debugging. Hypertransport bus debugging.- Debug PCIe bandwidth issues.
May 2010 - Mar 2013
Principal Hw Engineer
- ASIC/Systems Engineering.- Bringup and validation of multiple ASICs and PCBs.- Pre and post silicon 5G and 10G SERDES testing and characterization.- Detailed Schematic and Layout reviews.- PCIe Gen2 bus/protocol debugging.
Jun 2006 - May 2010
Aug 2005 - Jun 2006
Senior Embedded Engineer
Pathscale, Inc.
- Diagnostics and Manufacturing Testing for Infiniband HCAs.- Hypertransport and Infiniband bus characterization.- HW/SW Co-Simulation.- 2.5G SERDES bringup and characterization.
May 2003 - Sep 2005
Consulting Embedded Engineer/Senior Engineer
Raza Microelectronics (Formerly Sisilk Networks)
- Diagnostics for switch fabric ASICs/PCBs.- Hardware Abstraction and Software Abstraction layers system software.
May 2001 - May 2003
Consulting Sw Engineer
- SW, Design Compiler extension to export constraints to IBM EinsTimer.- Physical Compiler extensions to extract RC information and back-annotate net delays for timing verification and optimization.
May 2000 - Jul 2001
Sep 1999 - Sep 2000
Consulting Embedded Engineer
- Diagnostics, Firmware for Fibre Channel Simulator Card.- Architecture Simulation SW for Fibre Channel Switches, Adapters, Clients, Servers.
Dec 1997 - Jul 1999
Consulting Manufacturing Test Engineer
- Manufacturing Test Engineering for Medical Instruments - CT, MRI, Ultrasound Injectors.
Jan 1995 - Oct 1997
Sw Engineer
Antaire Corporation
- Nursing Home SW.- Financial SW (A/R, A/P, Inventory/Customer Management).- Automated Personnel Scheduling SW.
May 1991 - Nov 1994
1 education record
Raj Menon education
-
University Of Pittsburgh
FAQ
Frequently asked questions about Raj Menon
Quick answers generated from the profile data available on this page.
What company does Raj Menon work for?
Raj Menon works for Dell Technologies.
What is Raj Menon's role at Dell Technologies?
Raj Menon is listed as Technical Staff, Office of ISG CTO @ Dell Technologies at Dell Technologies.
What is Raj Menon's email address?
AeroLeads has found 1 work email signal at @tintri.com for Raj Menon at Dell Technologies.
Where is Raj Menon based?
Raj Menon is based in San Francisco Bay Area, United States, United States while working with Dell Technologies.
What companies has Raj Menon worked for?
Raj Menon has worked for Dell Technologies, Sima.Ai, Argo Ai, Apple, and Redwood City Police Department.
How can I contact Raj Menon?
You can use AeroLeads to view verified contact signals for Raj Menon at Dell Technologies, including work email, phone, and LinkedIn data when available.
What schools did Raj Menon attend?
Raj Menon holds Ms, Ee from University Of Pittsburgh.
What skills is Raj Menon known for?
Raj Menon is listed with skills including Asic, Device Drivers, Hardware, Compilers, Firmware, Systems Design And Engineering, Storage, and Automation.
Find 750M verified contacts
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trial