Matthew Gann Email and Phone Number

Worked on Software Defined Radio project as the Technical LeadDeveloped and configured custom embedded Linux distribution for the Xilinx XC706 Zynq development board based on the Yocto Project Build System toolsArchitected and began development of an Arbitrary Waveform Generation module for Xilinx Zynq FPGA to interface with an Analog Devices AD9361 RF Agile Transciever

Wrote a Python software tool to perform a quick data analysis in time and frequency domain of captured data to verify signal integrityDeveloped an FPGA VHDL design to perform data capture on multiple channels, packetize data, and transmits the data stream out Gigabit Ethernet at rates of over 300 MbpsDeveloped software for an Arm A9 embedded in the Xilinx Zynq SoC FPGA to support a new product verticleDeveloped complete software solution for next generation Solar Radio Control Module, including STM8 microcontroller, and Synapse RF200 Python scriptDeveloped complete software solution for an STM8 based microcontroller on a new Solar Arcfault Monitoring SystemAutomated conversion and upgrade script for Synapse E10 Linux systems to Solar Recombiner systemsAdded features and supported Python based calibration system for mesh network Solar Sensor Control Modules

Architected a replacement GMLRS Health Monitoring System design which eliminated shortcomings of the original system designWorked with a team designing the next generation Health Monitoring System for the Patriot Missile System, including architecture work, schematic entry, board layout, and part selectionImproved Windows application communications speed and reliability when interfacing with the Army GMLRS Health Monitoring SystemAdded features and maintained firmware for the Atmel ARM7 microcontroller and Freescale Coldfire microcontroller on the GMLRS Health Monitoring SystemMaintained Windows QT-based GUI interface for multiple GMLRS Health Monitoring Systems used by the U.S. ArmyDeveloped a Windows application to communicate with all versions of the HELLFIRE Missile System Health Monitoring Units

Project lead for feature enhancement of flagship power metering productSpecified microcontroller upgrade path to enable new featuresCoordinated efforts of engineers changes to the power metering productAnalyzed and implemented code optimizations to enable advanced feature additionsPlanned software development and projections for a new market need for the product, including register redistribution, alarm systems, and changes to the LCD GUI interfaceDeveloped Python based tools to communicate via Modbus interface for configuration and status monitoring of productsUsed the Modelsim tool to simulate and verify VHDL design elementsArchitected and developed Altera based FPGA framework for the newest development product line, incorporating multiple communications methods with various ICs, register control systems, and board support functions

Design Engineer* Member of a team of engineers developing field-programmable gate arrays (FPGAs) for many product lines in the company* Developed, simulated, and implemented Xilinx FPGA designs with ADSL, sHDSL, 10/100BaseT, and Gigabit Ethernet interfaces using ModelSim or Riviera-Pro and the Xilinx toolchain* Worked with a group of engineers designing and developing microwave radio products in the unlicensed 2.4 GHz and 5.8 GHz frequency spectrum* Lead Engineer for Ethernet point-to-point radio. Architected system design and developed the data mutiplexing and framing Xilinx FPGA* Developed and simulated framing and multiplexing schemes for both TDM and packet based systems using Mathcad, Matlab, and Python* Developed and implemented system provisioning and interprocessor management communication in a multiprocessor system using C++ for Motorola 866 processors* Wrote primary system tasks, menu interfaces, and CLI interfaces to setup and maintain data interface ports using C on embedded Motorola 860/866 microprocessors* Developed device drivers for multiple TDM framers using C on Motorola 860 and Philips 80C51 embedded microprocessors* Implemented a Cordic algorithm based carrier recovery loop in a mixed VHDL and schematic environment for a Xilinx FPGA