LPDDR5/4/4X PHY Product Line Owner and Project Engineering Manager responsible for advanced mixed-signal IP whole-product development from initial customer engagement through product design and final product release.• Responsible for managing the development of the LPDDR5/4/4X PHY architecture and several state of the art technology specific IP ports.• Successfully managed product development and delivery of multiple DDR PHY IP releases implemented in advanced foundry technology nodes to a large world-wide customer base.

Held various Engineering and Senior Engineering Manager positions, responsible for delivering Microprocessor and SOC IP from initial design concept through product release.• Led team to deliver logic design, validation, and physical design for 10nm Server Chassis IPs through design milestones.• Led the Kittson Itanium processor development project, including RTL development and verification, and physical design and verification.• Led team of 25+ design engineers and managers to deliver the RTL, validation, and physical design for Haswell Xeon Server uncore from initial design complete and into production.• Led a team of 20 design engineers and managers to deliver the global physical design and full-chip integration of the Poulson Itanium microprocessor design, including completing and delivering the final design databases to manufacturing for initial and post-silicon steppings.• Led a team of 30 engineers and managers to deliver the physical design of Tukwila Itanium microprocessor uncore, including the memory controller, cache coherence unit, test unit, and utility section from design concept through product release.• As member of MMDC Staff, collaborated with the MMDC group manager and staff peers to help set the strategic and operational directions of the group. Led several organizational objectives, including driving improvements in employee and manager development and cross-site design collaboration effectiveness. Actively drove continuous efficiency improvements through the use of Lean/Agile methods. Performed continuous meritocratic employee performance management.• Recruited, interviewed, and hired recent college graduate and experienced physical design and validation engineers while exceeding Intel’s diversity goals.

Delivered the physical implementation of multiple sections for the Alpha EV8, EV7 and EV6 microprocessor designs. Delivered completed designs, including feasibility analysis, circuit and schematic design, layout design, timing analysis, and electrical analysis. Also performed scheduling, resource allocation, mentoring, and coaching

Led the implementation of the Alpha LCA4s and LCA45 custom VLSI microprocessor development projects.Delivered a digital phase locked loop based decoder for a DEC Ethernet controller.Delivered the full design of an encoder chip for a 1 Gbit/s fiber optic link including design feasibility, micro-architectural refinements, floor planning, logic and circuit design, verification, and test vector generation.Designed configurable RAM and PLA megacells. Led development of automated array assembly and netlist generation tools that were used on several DEC chips. Designed configurable four-phase clock generator cell that was used on several DEC chips.Circuit designer for gate array and standard cell families. Successfully completed 2 gate array applications for a major military contractor with full first-pass functionality.

Circuit designer for gate array and standard cell families. Successfully completed 2 gate array applications for a major military contractor with full first-pass functionality.