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Semiconductor executive with diversified experience in managing BUs, large multi-geo engineering teams, product marketing, AE/BD teams and more importantly bringing products to marketIn-depth technical experience on Semiconductor IP, SoC/ custom ASICs, High-Speed PHY/SerDes, IOs, LibrariesPassionate about Product Marketing and Product Management, Go-to-Market Strategy, Business Planning, Partnerships, Licensing, and Application EngineeringExecuted 50+ ASICs and 100+ IP developments with various levels of complexity across geometry nodes
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Exploring New IdeasSelf EmployedCalifornia, United States
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Executive Vice President And Gm, Custom Silicon And IpAlphawave SemiCalifornia, United States -
Svp & Gm, Custom Silicon And IpAlphawave Semi Sep 2022 - PresentToronto, Ontario, Ca -
Sr Vp And Gm, Openfive Business UnitSifive Jan 2021 - Aug 2022Santa Clara, California, Us -
Sr Vice President & General Manager, Ip BuSifive Jul 2020 - Dec 2020Santa Clara, California, Us -
Vice President & General Manager, Ip Business UnitSifive Sep 2018 - Jul 2020Santa Clara, California, Us -
Sr Vice President And General ManagerOpenfive Jan 2021 - Jul 2022Milpitas, California, Us -
Sr. Director, Memory And Interfaces ProductsRambus Jan 2016 - Oct 2018San Jose, Ca, UsHigh Speed SerDes and Interfaces IP Cores Product Marketing and Management, Product Roadmap, IP definition, Sales and Business Development, Strategy, Customer Management -
Director, Product Marketing, High Speed InterfacesRambus Jan 2015 - Jan 2016San Jose, Ca, UsHigh Speed SerDes and Interfaces IP Cores Product Marketing and Management, Product Roadmap, IP definition, Sales and Business Development, Strategy, Customer Management -
Director, Asic Ip Solutions & MarketingOpen-Silicon, Inc. Jun 2010 - Jan 2015Bangalore, Karnataka, InLed the ASIC IP function and various SoC/ASIC Projects for Large, Mid and Start-up companies both in public/private spaceLed the SerDes Center of Excellence Strategy for High End Networking Requirements (10G/28G/56G) Responsibilities include definition of the ASIC IP solution in Pre-sales, IP/Vendor selection Procurement, Risk assessment, Qualification, Integration and First level of Application Engineering SupportPartner actively with all IP vendors/Foundries in semiconductor market for their offeringsManaged a team of Experienced IP Application Engineers to support various programs and customers on daily basisDefine methodology for improvement of processes for successful IP Integration and IP benchmarking activities -
Team Lead- Ip Qa And Application Engineering, Project Lead For Interface ProjectsInfineon Technologies Sep 2007 - May 2010Neubiberg, München, DeManaged IP Global QA and AE teams for IOs, standard cells, Memory compilers(SRAM/RF) libraries across all nodes and platforms.Led a team of 5 experienced people involving Resource planning, decision making, strategic planning etc.Project Lead for design of chip Interfaces like FS-USB, High Speed LVDS and other specialty I/O's across 250-40nm technologies.Project Lead for Analog/IP Design Migration Methodology Development: Led a sub team of SoC design Migration team inside Infineon to migrate existing IP designs to other nodes/process variants with quick TAT. Led the team on Analog/IP part of migrations and explored vendor offerings in market(Mentor, Wipro, Sagantec, Cadence)/internal solution for the same with a test for USB2.0 from 90nm to 65nm. -
Senior Design And Application EngineerInfineon Technologies Jun 2005 - Aug 2007Neubiberg, München, DeWorked with various product line(wireline and wireless) teams from definition stage till the final implementation and successful results of multiple interface projects.Goal is to provide cost and area optimized solutions by using right set of interfaces and other IP components.Dealing with external and internal IP's. Plus responsibility as a Project Lead for various Interface Projects.Design and application engineering of crystal oscillator IO pads(on chip real time 32kHz and MHz clocks) for wireline/industrial/wireless chip products. -
Project EngineerStmicroelectronics 2004 - 2005Geneva, Switzerland, ChWorked on design of various high resolution DACs for multiple applications in CMOS 90nm LP Technology
Mohit Gupta Education Details
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Indian Institute Of Management, CalcuttaExecutive Mba Program In International Business -
Birla Institute Of Technology And Science, PilaniMicrolectronics -
Thapar Institute Of Engineering & TechnologyElect. & Comm -
Dav Public School Ambala City
Frequently Asked Questions about Mohit Gupta
What company does Mohit Gupta work for?
Mohit Gupta works for Self Employed
What is Mohit Gupta's role at the current company?
Mohit Gupta's current role is Exploring New Ideas.
What is Mohit Gupta's email address?
Mohit Gupta's email address is mo****@****ail.com
What is Mohit Gupta's direct phone number?
Mohit Gupta's direct phone number is +4413552*****
What schools did Mohit Gupta attend?
Mohit Gupta attended Indian Institute Of Management, Calcutta, Birla Institute Of Technology And Science, Pilani, Thapar Institute Of Engineering & Technology, Dav Public School Ambala City.
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