2011-2014 : Verification lead for Cortex-A57, an ARMv8 power-efficient, high-performance, out-of-order, multi-processor micro-architecture. Responsible for planning/managing all aspects of CPU verification – unit, top, system, and formal testplanning and execution, creating and maintaining schedule, continuous improvement. Led a team of 20 in Austin, 8 in Bangalore2008-2011 : Verification lead for Cortex-A15. Responsible for all planning/managing all aspects of CPU verification. 2005-2007 : Individual Contributor on Cortex-A8 verification team. Owned a unit level testbench environment for the SIMD decode,issue, and execution pipes. Created a top level ISSCompare flow, created, ran, and debugged directed and random test in a top level environment. Implemented and closed coverage in multiple environments.2003-2004 : Wrote Verilog for SIMD datapath – integer multiply, add, and shift2002-2003 : Wrote a perl-based Verilog pre-processor for use by the RTL team. Some features : automatic creation of flops, muxes, and other regular structures, lint-checking, auto-declaration generation

Bringup, maintenance, debug of an FPGA platform based on an ARM ‘Integrator’ boardRTL development of a hardware-based data decompressor RTL development of a ASB-to-AHB bridge for use in the FPGA platform