Michael Doyon Email & Phone Number

I'm a highly motivated recent Electrical Engineering graduate with a passion for computer architecture and digital logic design. Currently looking for roles within the ASIC/FPGA domain or verification engineering. I have experience in various HDL languages including Verilog, VHDL, and SystemVerilog and have used verification tools including VCS, Verdi, and UVM. Over my time at UCF, I've honed my skills in the world of digital logic design with various projects and coursework directly related to RTL and verification industry practices.