Michael Penner Email & Phone Number

Burnaby, British Columbia, Canada

Chip Lead- Led technical efforts for the META-DX2L (1.6Tbps Ethernet PCS PHY), bringing a 112Gbps integrated SerDes to production quality.- Cross-functional technical leadership of a small team through silicon validation and characterization.SerDes Integration Technical Lead- Leading a second 112Gbps integrated SerDes to production quality on a related program.

Burnaby, British Columbia, Canada

Padring Design and Packaging Cross-Functional Lead- Delivered four flip-chip package designs on-time for Terabit Ethernet products.Power Czar- Led business unit’s development of 1GHz+ chip low-power design flow, reducing chip wasted power 75%, implementing macro- and micro-architecture low power techniques. Awarded discretionary bonus.Flow Automation- Designed automation for corporate-wide use in padring design, power reporting, and STA results analysis.Languages: Verilog, Perl, Makefile, Bash, TCL, CPFCadence Toolchain: Incisive/NCSim, Genus, OrbitIO, Joules, Cadence Low Power, LEC

Richmond, British Columbia, Canada

Set Top Box DFT- Owned chip-level DFT for two best-in-class, prolific chips by generating and verifying scan, LBIST, and MBIST patterns and being responsible for overall ATE success from bring-up to production release.Cellular Baseband SoC DFT (Malta, Aruba, TahitiP)- Responsible for business unit’s memory repair strategy by architecting, implementing, verifying repair on flag-ship product while authoring manual and mentoring colleagues. Led cross-functional co-operation with firmware, power intent, and functional verification teams.- Inserted LBIST/MBIST on several blocks using advanced techniques such as hierarchical (macro within a macro) insertion and mixed RTL/gates insertion.Cellular Baseband SoC DFT Technical Lead (Capri)- Responsible for overall DFT success of the chip, soundness of DFT architecture, development of the block and chip-level DFT LBIST and MBIST flows, DFT security, mentoring of junior engineers.- Responsible for post-silicon efforts to production release: pattern generation, silicon bring-up, development of speed-binning and DVFS patterns, cross-functional interactions with operations and test engineers.

Richmond, British Columbia, Canada

Cellular Baseband SoC DFT Technical Lead (BigIsland)- Led chip DFT, responsible for chip-level DFT architectural implementation including controls, clocking, resets under extreme time pressure.- Integrated DFT for the most complex IPs: multimedia, GHz ARM processor.- Integrated analog test for PHYs, SERDES, ADC/DAC and monitors.VoIP SoC DFT Technical Lead (BCM11107)- Awarded top yearly performance of 25-member business unit team for overall chip production DFT success by single-handedly owning all aspects of LBIST-based flow and accomplishing quick silicon pattern bring-up. Responsible for DFT architecture, much of the implementation, and overall success from inception to production release. Designed DFT control, clocking, resets, and inserted LBIST, MBIST, scan top-up and boundary scan.Tools: Tessent (scan, LBIST, MBIST), Synopsys (DC, PrimeTime, Formality), Cadence Incisive/NCSim, Verdi, Spyglass, JasperLanguages: Verilog, Perl, TCL, Bourne-shell, Makefile, BSDL

Burnaby, British Columbia, Canada

- Coded and verified firmware for SoC with embedded MIPS processor.- Specified, coded, and verified PCI Host driver for Linux 2.6.- Designed and coded interrupt-driven direct memory access (DMA) driver.

Burnaby, British Columbia, Canada

PCI Host Bridge Development- Led hardware design of high-performance PCI Host Bridge for Cisco-sponsored SoC.- Architected design, integrated delay-locked loop for high-speed I/O timing.- Synthesized using fine-grained clock gating techniques, inserted scan and analyzed static timing across multiple clock domains.T1/E1 Communications Chip Lead- Chip lead for one of the company’s most prolific products. Led a small team facing strict market demands for customer availability, package size and cost.- Awarded 15% raise for proving leadership in carrying product through full development life cycle. Created chip development plan and schedule, architected and integrated top-level system, designed padring, authored chip engineering document, approved verification and validation plans, mentored junior engineers.SONET Framer Development- Specified requirements, implemented time-sliced design, performed synthesis, scan insertion, ATPG, static timing analysis, coded Perl testbench interface, oversaw verification.Tools: Design Compiler, NCSim, Mentor GraphicsLanguages: verilog, VHDL, C, Perl, linux shell scripting, TCLPCI Host Bridge Development

Burnaby, British Columbia, Canada

DSL Traffic Aggregation Chip Development- Achieved Rev A success and awarded 20% bonus on the design of two new transmitter/framer blocks by implementing, synthesizing, and verifying them under extreme market pressure.- Created and executed chip verification plan using highly randomized verification environment.Telecom Transmitter/Receiver Development- Led chip-level verification of company’s flagship COMET chip, creating and executing verification plan.- Designed, coded, verified and documented telecom blocks.