Michael Penner Email & Phone Number

Burnaby, British Columbia, Canada

Chip Lead- Led technical efforts for the META-DX2L (1.6Tbps Ethernet PCS PHY), bringing a 112Gbps integrated SerDes to production quality.- Cross-functional technical leadership of a small team through silicon validation and characterization.SerDes Integration Technical Lead- Leading a second 112Gbps integrated SerDes to production quality on a related.

Burnaby, British Columbia, Canada

Padring Design and Packaging Cross-Functional Lead- Delivered four flip-chip package designs on-time for Terabit Ethernet products.Power Czar- Led business unit’s development of 1GHz+ chip low-power design flow, reducing chip wasted power 75%, implementing macro- and micro-architecture low power techniques. Awarded discretionary bonus.Flow Automation.

Richmond, British Columbia, Canada

Set Top Box DFT- Owned chip-level DFT for two best-in-class, prolific chips by generating and verifying scan, LBIST, and MBIST patterns and being responsible for overall ATE success from bring-up to production release.Cellular Baseband SoC DFT (Malta, Aruba, TahitiP)- Responsible for business unit’s memory repair strategy by architecting, implementing.

Richmond, British Columbia, Canada

Cellular Baseband SoC DFT Technical Lead (BigIsland)- Led chip DFT, responsible for chip-level DFT architectural implementation including controls, clocking, resets under extreme time pressure.- Integrated DFT for the most complex IPs: multimedia, GHz ARM processor.- Integrated analog test for PHYs, SERDES, ADC/DAC and monitors.VoIP SoC DFT Technical Lead.

Burnaby, British Columbia, Canada

- Coded and verified firmware for SoC with embedded MIPS processor.- Specified, coded, and verified PCI Host driver for Linux 2.6.- Designed and coded interrupt-driven direct memory access (DMA) driver.

Burnaby, British Columbia, Canada

PCI Host Bridge Development- Led hardware design of high-performance PCI Host Bridge for Cisco-sponsored SoC.- Architected design, integrated delay-locked loop for high-speed I/O timing.- Synthesized using fine-grained clock gating techniques, inserted scan and analyzed static timing across multiple clock domains.T1/E1 Communications Chip Lead- Chip lead.

Burnaby, British Columbia, Canada

DSL Traffic Aggregation Chip Development- Achieved Rev A success and awarded 20% bonus on the design of two new transmitter/framer blocks by implementing, synthesizing, and verifying them under extreme market pressure.- Created and executed chip verification plan using highly randomized verification environment.Telecom Transmitter/Receiver Development- Led.