Michael Cada Email & Phone Number

Santa Clara, CA, US

Contract layout engineer (working remotely via Encore, 6/22-present), lead layout position responsible for floor planning, scheduling, training of junior layout engineers for Marvell’s 12nm PHY interface. This is a port from a 5nm design in TSMC’s process. Tasks included lay out of pad cells, high speed digital, chip-level (bump) design and placement, and.

Hyderabad, TS, IN

Full time layout engineer, working remotely for the following customers:Global Foundries, Raliegh, NC - Contract layout engineer (1/2016-present), designed analog circuitry in GF's 14 & 7nm process. Worked with GF's team to bring up their 7nm process, including developing a standard cell library and generating test structures. Most recently designed.

Santa Clara, California, US

Laid out custom cells for memory arrays and mixed signal circuits untilizing Global Foundries 14nm process.

Austin, TX, US

Palo Alto, California, US

Performed layout and project management tasks related to complex CMOS analog design, Power Management chip design, test chip assembly and IP development. Lead layout designer; responsibilities included scheduling, architecture design, resource management and project definition. Trained numerous engineers and layout desigers in best layout practices, tool.

Santa Clara, California, US

Job responsibilities included layout and verification of Intel’s cell library, and top-level block planning and assembly. Other tasks included, redesign of existing cells for robustness and reliability.

Santa Clara, CA, US

Performed custom I/O cell design and custom layout development for Agilent's workstation microprocessors in TSMC’s 0.13um and 90nm technologies. Responsibilities included specification definition, scheduling, design, simulation, layout, verification, and documentation. Other job functions included cross-checking other designer's artwork, automation (via.

Completed layout of I/O pads for the PortalPlayer program ahead of schedule; which included included floorplanning, project verification and integration.

San Jose, CA, US

Primary responsibilities involved the design of custom, high speed (2.5-3Ghz) analog blocks, including PLL’s, drivers, differential receivers, bias circuitry, etc. Additional duties included floorplanning, project planning, verification, and integration.

Milpitas, CA, US

Job duties included datapath layout, including layout of basic digital building blocks, and verification.

Santa Clara, CA, US

Contract IC Design/Layout Engineer - Job duties and accomplishments were identical to contract position held later at Agilent Technologies.

Custom and strategic I/O designer, which includes specification scheduling, specification definition, design, simulation, layout, verification, characterization, documentation, QA and release to LSI Logic's third party model development organization. 9/1996 - 10/1998 Symbios Logic - Fort Collins, CO IC Design Engineer Performed key role in the development.

Bachelor Of Science (Bs), Electrical And Electronics Engineering

Education record