Michael Chambers, Pmp Email & Phone Number

Austin, Tx, Us

Bloomington, Minnesota, United States

Frisco, Texas, United States

Project Manager - Secure Transactions and Identification

Dallas/Fort Worth Area

Promoted to organize and direct project teams to include oversight of project scope, schedule, cost and resources to meet key milestones. Led weekly team meetings, including customer teams to review project actions, schedules and track expenses. Facilitated meetings with stakeholders to provide status updates. • Oversaw budgeting, invoicing, purchase orders and requisitions and accounts payable.• Developed project plans aligned with Product Lifecycle Management (PLM).• Prepared and presented project slides in monthly business operations reviews and documentation for production release of products. • Maintained project deliverables in Agile Configuration Management System.• Supported certification and customer audits.• Forecasted and tracked materials for both wafer fab and assembly process.• Developed lessons learned and continuous improvement database using SharePoint.• Held and maintained government security clearances. • Managed ~35 projects. Some recent projects includeo 65nm shuttle with 28 test chips to enable process in newly purchased fab. One of the test chips was an analog IP test chip to validate multiple analog blocks needed by end customer. Other test chips included SERDES, DDR, RadHard test chip and many more.o 110nm project for 5G infrastructure. Project required starting 450 wafers during development in order to fill pipeline for early production shipments.o 180nm SoC design with interposer, ASIC, Voltage Regulator and capacitors in package. ASIC included ADC, RAM and ~600K gates. Custom package development required.o 180nm Aerospace project requiring 3.3V core for drop-in compatibility. DO254 support required.o Designs were mostly digital with RAM/ROM. Some incorporated ADC, DAC, PLL. Considered Big D, Little A (Big Digital, Little Analog). A couple designs included ARM7TDMI. Technology nodes ranged from 0.35um to 65nm. Most were military, aerospace, or industrial applications with some commercial and automotive.

Provided project and customer management support. Delivered training to teams on use of Artemis Project Management Software. Semiconductor digital design engineer with over 40 tape-outs.Specialized in Design-for-Test (DFT) including SCAN, JTAG, MBIST, and IP Integration. Skills also include Static Timing Analysis (STA), Logic Equivalence Checking (LEC), Testbench and Test Pattern Generation, and software flow automation using Perl, sed, and Shell Programming.Projects includedo 110nm 175 MHz Aerospace chip with DO254 requirements. 1.4 million gates and 1152 ball FCBGA package. Was DFT lead engineer. Included Digitally Controlled Impedance (DCI) IO’s requiring both functional and impedance testing for the analog finger tests. DCI controller required test logic and test patterns to fully test. Designed and implemented all control logic and wrote test patterns for all tests. With DO254 requirement, required full documentation of how every item was tested and by which pattern. Worked with test engineer to ensure all items tested and characterization report received and analyzed to ensure compliance.o 0.8 micron consumer electronics Mixed Signal device - Worked with Mixed Signal team supporting digital design work for various digital blocks which were incorporated in the mixed signal design.o Majority of designs were digital with RAM/ROM. Some incorporated ADC, DAC or PLL. Considered Big D Little A (Big Digital, Little Analog). Technology nodes ranged from 0.8um to 110nm.

Tested and diagnosed problems in avionics and electrical systems.