Michael D. Powell Email & Phone Number

Greater Boston

Product architect for Intel® Xeon® 6 Processors with Performance-Cores (codename Granite Rapids) from product conception to launch. The modular architecture of Intel® Xeon® 6 Processors enables multiple SoC’s across two platforms that together provide increased core count, memory bandwidth, and I/O capability. Led Granite Rapids through major technology direction changes during pathfinding. Architected features for performance, reliability, and survivability, and delivered quality documentation to support pre-silicon and post-silicon execution. Executed new process for high-quality requirements grading. Drove delivery of late feature requirements during execution and post-silicon. Provided internal and external customer overview of Intel® Xeon® 6 Processors.

Greater Boston

Product architect for Intel® Xeon® 6 Processors with Performance-Cores (codename Granite Rapids)

Greater Boston Area

Architect for Intel® Turbo Boost Max Technology 3.0 introduced on 6th Generation Intel® Core™ X-series Processors (codename Broadwell-E). Analyzed silicon data over multiple generations to determine performance potential of selecting the best core for turbo. Co-recipient of 2017 Intel Achievement Aware for driving this feature into Broadwell-E.Soft Error Architect for Knights Hill many-core SoC. Owned subsystem-level rollups of soft errors and guided usage of architecture and circuit mitigations.

Ph.D, Electrical And Computer Engineering

Activities and Societies: Eta Kappa Nu (Beta Chapter president, spring 1999), Tau Beta Pi

Bs, Electrical Engineering

Activities and Societies: Eta Kappa Nu, Tau Beta Pi