Michael Fredette Email & Phone Number

Hillsboro, Oregon

• Intel Labs, Quantum Computing Research Group, Radio Circuits Technology Division.• Full chip floor planning, full chip block integration, die file and package generation, full chip database tape-in delivery. • Layout on Intel 3nm, 5nm, 14nm LPFF, TSMC 16FF nodes, large RF analog circuits, mmWave circuits, 5G transceivers. PLL's, ADC/DAC's, LNA's, LDO's, Power Grids, inductor Coils/Baluns. • Cadence Virtuoso XL and Calibre verification tools

Gilbert, Arizona

Start up Air Ambulance company. Responsible for all administrative and managerial aspects of setting up the corporate structure, received AZ, NV, FL state air ambulance licenses and FAA Part 135 licensing and new STC approvals for hospital beds in Cessna Citation X, inventory control of medical supplies, vendor account set up, and managing day to day aviation operations for 2 Cessna Citation X business jets.

Chandler, Arizona

• Layout on 14nm FINFET /28nm of large analog circuits on various Smarti cellular transceivers• Layout on 14nm/1273 FINFET process. DDR IP product• Large macro owner, ddr_clkgentop (clock generator) Cadence 6.1.6 Virtuoso XL, Calibre tools• Interviewed MD/PDE team candidates, contract and direct. Supervision/mentoring junior MD’s

* Layout of Power Management IC’s (PMIC), Analog/Mixed Signal, RF Sensors, MEM’s, radar, for automotive and consumer/industrial products.* Cadence Virtuoso and Virtuoso XL, ASSURA, Mentor/CALIBRE, Cadence 6.1.5 OA, Cadence 5.1./4.4.3 and 4.3.4* TSMC 28nm, 55nm, 65nm, 180nm, FSL SmartMOS5, SmartMOS8MV/LV, HIP6, CMOS90 SmartMOS10

Boise Id

* Layout of DDR2, DDR3, RLDRAM, SRAM, PSRAM, L2 Caches for various memory projects. Scheduling and supervision of other mask designers. * Planning and layout of large blocks on numerous DRAM projects, custom sense-amps, decoders, pad-ring, I/O structures, array core, data path, clock circuits. * Cadence Virtuoso/Hercules/Avanti tools for layout and verification.

* Audio CoDec/DSP, analog mixed signal, ADC/DAC, data path, supervision/mentoring junior mask designers. Cadence/Hercules tools, clock trees, op-amps, AD/DA circuits . * Willamette MP (Pentium 4), Cluster owner, Unit owner. Planning and layout of multiple units and large data path blocks, using Cadence and Intel (CHPPR/DLS) tools.* Deschutes MP (Pentium 3), Merced MP (Pentium 3), Unit owner. Planning and layout of large data path units, Cadence & Intel tools Unit, Co-development and… Show more * Audio CoDec/DSP, analog mixed signal, ADC/DAC, data path, supervision/mentoring junior mask designers. Cadence/Hercules tools, clock trees, op-amps, AD/DA circuits . * Willamette MP (Pentium 4), Cluster owner, Unit owner. Planning and layout of multiple units and large data path blocks, using Cadence and Intel (CHPPR/DLS) tools.* Deschutes MP (Pentium 3), Merced MP (Pentium 3), Unit owner. Planning and layout of large data path units, Cadence & Intel tools Unit, Co-development and college instructor IC Mask Design course at Mesa Community College, Mesa, Arizona.* P6 MP (Pentium 2), Unit owner, Planning, layout of large units, large SRAM arrays Show less