Michael Kirkpatrick Email and Phone Number
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ASIC design engineer and implementation lead experienced in developing complex SoCs for the consumer, video imaging and other markets. Highly regarded team player, recognized for leadership, initiative, and ability to drive tasks to completion with accurate and reliable results. Proven ability to multi-task in a fast paced environment while maintaining high quality of results and meeting project deadlines.Experienced in all phases of physical design including RTL handoff, synthesis, floorplanning (regions/preplacement/pin optimization/congestion avoidance), hierarchical block bus/pin planning, clock tree synthesis, place and route, timing optimization, parasitic extraction, static timing analysis, timing closure, IR drop analysis, signal integrity checking/correction, logical equivalence checking, DFM compliance, physical verification and sign off.
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Director Of EngineeringMarvell SemiconductorWestborough, Ma, Us
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Director Of EngineeringMarvell Semiconductor Jul 2018 - PresentSanta Clara, Ca, Us -
Consulting EngineerCavium Inc 2016 - Jul 2018San Jose, California, Us -
Principal Design EngineerToshiba 1998 - 2016Minato-Ku, Tokyo, JpPERSONAL AND TECHNICAL HIGHLIGHTS- 20+ years of SoC RTL to GDSII expertise - Track record of successful first pass SoCs tape-outs- ASIC/SoC physical design expert - Hierarchical design implementation team lead- Core limited IP/SRAM complex floorplans - Clock tree synthesis specialist - Designed robust power distribution schemes - Fluent in top-down planning/bottom-up implementation - Power sensitive design implementation. - Multi-voltage domain designs - Internal/external IP integration - Timing constraint generation/analysis/validation- STA/timing closure expert - Customer block performance benchmarking evaluation- On-chip signal integrity analysis and closure - Logical/physical verification - Post-silicon timing debug/mask ECO- Methodology flow development/TAT improvement- Primary technical contact for TAEC’s tier one customers- Mentor to TAEC’s contract workers TOOLS AND LANGUAGESDesign Analysis: Synopsys Spyglass Lint/CDC, Excellicon ConMan/ConCertSynthesis: Synopsys DC/DCT/DCG, Magma BlastCreate, Cadence AmbitTiming Closure: PrimeTime-SI/DMSA/AOCVPlace & Route: Synopsys Talus/BlastFusion/ICC, Cadence FirstEncounter/WarpPhysical Verification: MentorGraphics Calibre DRC/LVS/ERC/ANTLogical Verification: Conformal LEC/CLP, Synopsys FormalityOther: Virtuoso, NC-VerilogLanguages: TCL, UNIX scripting (perl/awk/sed), Python, Verilog, C/C++, Make, Microsoft Office -
Principal Design EngineerDigital Equipment Corp 1987 - 1998Houston, Texas, UsKey member of the Digital ASIC center focused on defining and implementing methodology flows providing support to the Digital ASIC design community. Technical and team lead for development of internal EDA tools (GUI Floorplanner/Partitioner) and design flows. Used third-party EDA tools to create a highly integrated design environment. Worked with team on establishing the Digital Semiconductor COT Foundry model.Interfaced with internal DEC ASIC designers to address design issues ranging from synthesis, optimized scan hookup, floorplanning/partitioning, timing analysis/closure, physical layout and verification using internally developed EDA and third-party tools. Ensured conformance to design requirements and customer design schedule.
Michael Kirkpatrick Skills
Michael Kirkpatrick Education Details
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Rochester Institute Of TechnologyComputer Engineering -
Georgia TechElectrical Engineering
Frequently Asked Questions about Michael Kirkpatrick
What company does Michael Kirkpatrick work for?
Michael Kirkpatrick works for Marvell Semiconductor
What is Michael Kirkpatrick's role at the current company?
Michael Kirkpatrick's current role is Director Of Engineering.
What is Michael Kirkpatrick's email address?
Michael Kirkpatrick's email address is mi****@****ast.net
What schools did Michael Kirkpatrick attend?
Michael Kirkpatrick attended Rochester Institute Of Technology, Georgia Tech.
What skills is Michael Kirkpatrick known for?
Michael Kirkpatrick has skills like Asic, Static Timing Analysis, Timing Closure, Soc, Physical Design, Ic, Semiconductors, Verilog, Eda, Tcl, Floorplanning, Cmos.
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