Michael Lerer Email & Phone Number

Herzliya Area, Israel

RDC CAD owner - developing RDC flow, working with the vendor on bug fixes,enhamcements and new features definition and deployment. Providing support for teams across the globeLint and CDC CAD co-owner - Close work with design team and vendors on new rules definition and enhancements. Providing support for teams across the globeFormal Equivalence - Driving project LEQ convergence for dozens of partitions, working on HV and aborts resolution with vendors.ECO flow - maintaining ECO flow and providing support for designers for both manual and Conformal ECO

Haifa Area, Israel

2014 - 2015 Spyglass LP owner providing support for IP and partition owners, definingnew rules and methodology. As UPF expert supported IP and global feature owners for IPs UPF preparation and integration into partition. Defining methodologies and flows for UPF generation. Own the flow uArch spec -> UPF. Own flows and supporting in-house solutions for LP design.2011-2013 LP CAD methodology owner & FE LP IPs onwer  key member in LP working group while defining methodologies, owning LP System Verilog macros, LP structural checks execution, driving global activities such as LP cleanup of the design, LP paranoia and LP TI checklist.  Power Switch and Power MUX IPs FE owner in SKL project, including definition and integration into FC. Close work with BE designers, partition owners and Power Management team.2007-2010 FE CAD engineer and LP convergence owner  Drove CPU LP design convergence both in FE and BE domains, working closely with designer and providing support for US FC team.  Moved to FE DA team, while fast ramp-up on FE tools defined and implemented first Intel FE LP checker on top of existing SV compiler, helped with H&C FE tool enhancements and fixes, implementing newfeatures in registers uArch->RTL tool.2006-2007 Working as BE CAD engineer  Developing features for PnR and circuit tools, providing support for circuit and physical designers.  Owned several areas like power network connectivity, automation of schematic and placement generation of various IPs like adder, one-hot, muxes. Owned gnac and tap insertion flows and more.