ARM Architecture L0/L1 Design Technical Lead (2003 – Present)For Multi-Generation Award Winning Snapdragon and Data Center Centriq 2400 Chip Sets• Led a team of engineers to design the micro TLBs, L0/L1 arrays for data and instruction caches in bulk CMOS 65nm, 45nm, 20nm and FinFet 16nm, 14nm, 10nm, 7nm.• Designed SRAM, CAMRAM, Set-Prediction SRAM custom high-performance arrays for both data and instruction caches;• Proven high quality array design for different generations of various SnapDragon and Data Center Centriq 2400 chip sets; seamless integration with hardware• Collaborated with CPU logic designers/architects to invent circuit architectures for various memory array structures and analyzed the complete solution.• Partnered with SnapDragon and Data Center Centriq 2400 product test teams to develop HW qualification characterization plan; collected and analyzed characterization data for all CPU arrays across all different process technologies; identified and solved issues which enhanced design quality • Worked with QCT technology team and different foundries to develop 6T, 8T, 10T and CAM memory cells to improve area and circuit performance

Reviewing submitted papers.Working with the presenters on their papers.performing ISSCC Session chair duties.

• Designed and led a team to do various data/instruction cache sizes for different Power Embedded PC chip sets in CMOS technology. Designs such as SRAM array and first in the industry 4-Way set-predicted CAMRAM, 16-Way CAMRAM • Collaborated with architects/ logic designers and DFT team to make sure that the design met all specs and testable