Senior Technical Leader
CurrentTeam member delivering four ASIC Networking and Industrial Ethernet architectures with over twenty ASIC variants, using 120nm down to 5nm technology nodes, primarily with ASIC vendors, most recently utilizing internally developed COT flows, targeted for the Catalyst product line. These efforts yielded over 30 million units shipped and brought in an excess of $10B in annual Cisco product revenue. Some of the resulting products won the Cisco Pioneer Award for Innovation twice and were a Finalist once.Key leader and technical contributor to the development of multi-terabit wired and wireless enterprise ASICs, carried from market requirements through production release. Architect and hands-on RTL designer of major datapath and forwarding controller modules, as well as chip level pre- and post- silicon verification. Performed design tasks such as timing analysis, assertions, test plan creation, coverage analysis, low power design, emulation, and script writing.Full chip integrator of multiple ASICs, interfacing with different ASIC vendors (Broadcom, Avago, LSI Technology, IBM, Renesas, ST Micro and Texas Instruments). Responsible for integrating Cisco proprietary logic with vendor IP (PLLs, SerDes, PCIe, CXL, I2C, EMMC, USB, other Synopsys IP), chip floor-planning and signal/power integrity analysis. Experienced with embedded systems, TCAM and ASIC architectures.Led cross-functional teams to align ASICs, systems, software, diagnostics and vendor requirements. Cross-functional experience working with systems teams on ASIC integration issues: ASIC package design and qualification, I/O selection.Extensive lab experience working with diagnostics and software teams during system testing and product integration. Deep knowledge of lab equipment (logic analyzers, high speed scopes, packet generators, eDVT equipment).Granted U.S. patent for embedding packets within packets on a serial link.
