Responsible for Global corporate strategy for yield and engineering data analysis and systems to support fast yield ramp in development and high volume manufacturing environments.

Technical leader and program manager responsible for the development of several web based Yield management applications used by the product and fab yield engineers. Developed and implemented systems for automated find relationships, interactive wafer positional analysis, and Universal Spatial Pattern Recognition. All of the applications are part of the analytical suite used by the yield engineering groups in Germany and the United States.

Technical leader and project manager responsible for research related to defect detection capability in the semiconductor industry. Designed test vehicles and manufactured wafers of intentional defect arrays to evaluate the capabilities of leading edge defect detection equipment. Created unified specification with industry representatives to define the methods and metrics used to evaluate defect detection equipment. Evaluated the novel approaches to high aspect ratio defect detection including “Direct to Digital Holography” (DDH), micro-mechanical stress measurement, and compensation current e-beam measurement. Served as chairman for the International Technical Roadmap for Semiconductors (ITRS) responsible for the definition of the technology needs for defect detection and characterization.

- Technical leader for Yield management and enhancement responsible for CFM scan strategy and Yield management methodologies. Developed several WEB based Yield and CFM engineering software tools used by the Yield Engineers and Technicians. Assisted in the evaluation of Engineering Data Analysis tools for use across AMD and member of Engineering Data Analysis team. - Manager of CFM department consisting of 4 engineers and 20 technicians. Coordinated the consolidation of the Fab 14/15 CFM departments adopting best practices from each group. Developed and implemented in line defect control strategy for Wafer manufacturing line. Created “short loop” in line control schemes and metrics derived from Yield goals. Yield ramp time reduced and process defect stability established with this methodology. - Lead Engineer for Yield Enhancement on Flash and EPROM Devices. Leader of a team consisting of 4 engineers and 4 engineering technicians. Created several Yield Management software tools increasing productivity of engineering personnel with respect to experimental evaluations and Yield Analysis. Responsible for process centering to maximize yield and device performance on FLASH devices.

Advisory Engineer -Process Integration and Technology Development -Process and product integration of a 64M DRAM device built in a .35 micron CMOS technology. Developed and implemented several Yield modeling routines and defect/parametric yield loss ranking routines to drive fast yield ramp. Data analysis techniques to resolve several product performance, design, and process window sensitivities. Advisory Engineer, Yield Characterization- Lead Engineer responsible for Yield and reliability of a 4MB DRAM device in a .6um / 8” CMOS technology in a high volume manufacturing environment. Responsible for the execution of the Yield learning plan and methodology for the fab ramping the yield from 10% to >80% in 24 months. Developed several SAS based analysis routines to quickly determine and rank the Yield detractors in terms of process equipment and parametric set points in line. Yield methods developed were considered “Best Practice” for company and installed in Fabs in Germany, East Fishkill NY, and Yasu Japan. Co-authored two papers on Yield modeling that were presented at IEEE conferences during this time period.Staff Engineer, Bipolar/FET Yield Characterization- In line yield characterization of Bipolar SRAMS and FET logic parts. Job duties included Yield detractor analysis based on electrical test results, Physical Failure analysis, and in line inspection results. Supervised 3 technicians and coordinated efforts to perform electrical bench testing as well as physical failure analysis. Tracked major process changes and designed and evaluated process experiments. Associate Engineer, In lineTest Bipolar/FET SRAMS & Logic parts - Tester hardware and software support for in line characterization activities for high performance bipolar and MOS devices. Developed analysis software for a functional tester to perform Bit Maps, Mask Qualifications, and performance evaluations using APL and SAS programming language.