Michael Van Buskirk Email and Phone Number

Services include:-- Emerging non-volatile memory technology development and commercialization expertise-- Semiconductor memory market challenges and opportunities-- Flash and DRAM memories-- Competing emerging memory technologies-- Effective joint development partnerships – creation, and management-- Management, business and exit strategies-- Intellectual property: acquisition, patent re-examination and litigation-- Client specific special projects

Overview – Responsibilities include: all aspects of emerging memory technology development suitable for next generation enterprise data storage, joint development partnerships assisting the company’s technology development, and patent portfolio. Developing conductive metal oxide RRAM Joint development partnership with HGST (a Western Digital company)

Established strategic emerging memory (RRAM) market requirements, identifying 1st generation CBRAM™, Adesto’s proprietary RRAM technology, commercial limitations.Initiated, directed and qualified 2nd and 3rd generation CBRAM technologies, addressing factors which would significantly expand total available market by: -- Substantially improving high temperature data retention and thermal stability. -- Full process compatibility with standard DRAM and logic foundry processes.Adesto is one of only two companies to commercialize RRAM, with over 1 million 2nd and 3rd generation CBRAM units shipped in 1H14.Re-kindled and significantly improved external university research effectiveness leading to fundamental CBRAM (RRAM) cell stability understanding.Licensing, technology transfer and technical spokesman to DRAM and logic foundries.

Key operational and technical corporate officer throughout sale of Innovative Silicon: pre-sale corporate road-show, as well as facilitating asset and personnel transfers to acquiring company. Demonstrated DRAM-like retention using dual buried metal gate vertical floating body transistors with gate offset (Z-RAM™).Initiated and directed both DRAM vertical access FET and Non-Volatile floating body memory development.

Determined existing Z-RAM™ technology was neither scalable nor reliable. Co-invented ultra-low voltage floating body DRAM memory cell suitable for cost-effective bulk silicon stand-alone memory application.Re-ignited customer relationships by instilling confidence through integrity and innovation.Directed bulk silicon vertical floating body transistor technology development at Hynix. Achieved working arrays within 4 months of initial concept (included new process flow and test chip development).

Directed 32nm NAND technology and product architecture team, resulting in stringent 50% cost reduction, industry leading die size, and product performance with respect to 43nm node.Invented two industry leading NAND flash memory product architectures with an international (Japan, Italy, and US) team of more than 50 flash memory technical experts.Orchestrated Spansion/TSMC partnership to develop and commercialize 43nm ORNAND2™ (Spansion’s charge trap NAND) technology and products. Resulted in functional test product within 1½ years of initial technology concept.Restructured and transferred worldwide design and test engineering organization (more than 300 engineers) from corporate organization to the three respective business units,providing greater business and product creation autonomy.Co-directed, with Chief Scientist, advanced memory research and technology development focusing on resistive switching in conductive metal oxides.Initiated Advanced Package Development group to develop radical product architectures utilizing system-in-package (SiP), multiple memory die, mixed semiconductor technologies, and passives.

Integrated the former Fujitsu and AMD flash memory engineering teams into an efficient and effective international team with design centers in Sunnyvale, CA; Austin, TX; Dresden, Germany; Penang, Malaysia; Hong Kong, China; Kozoji, Japan; and Tokyo, Japan.Responsible for entire corporate technology strategy, product design and development, and future product architectures; notably: 1) ORNAND™ (MirrorBit NOR based product addressing NAND market) high reliability data storage products. 2) 1.8V MirrorBit™ Simultaneous Read/Write for wireless applications. 3) Initiated modular product design approach to facilitate maximum design reuse. 4) Produced 30-50 product designs per year.Initiated two year metal-organic material research with the Institute of Inorganic Chemistry, Russian Academy of Sciences, Siberian Branch, while directing internal ionic polymer and conductive metal oxide research.Sponsored development of industry’s first full wafer probe system capable of testing up to 3000 die in parallel with single touch-down while initiating a BIST (built in self test) development strategy reducing test cost by more than 50%.MirrorBit™ (Spansion’s charge trap NOR) technology development completely replaced their floating gate development after 90nm. MirrorBit™ became the basis for all Spansion’s future Non-Volatile memory products.