Michael Venditti Email & Phone Number

Montreal, Qc, Ca

San Jose, California, Us

Leading PCIe Gen 5 serdes development team

San Jose, California, Us

Chandler, Az, Us

Technical/Project Lead for 25.6Gb/s OpenCapi/OIF-28G-MR SERDES macro in 16ffc process. * Included selective porting and design/architecture modification (serializer/transmitter, ADC, clocking) of legacy 28nm IP and new architecting for select subsystems (RX AFE)* Interactions with internal BU units (technical + schedule) and with lead customer (technical)* Revision A prototype success; Revision B production release.Technical/Project Lead for 32Gb/s PCIe Gen 5 SERDES macro in 16ffc process. * Developed for use in PCIe switch and retimer applications* Included selective architecture modification (clock synthesis) of legacy IP and re-architecting of most subsystems (quarter-rate serializer/transmitter, RX AFE, ADC with 10 tap DFE and current integrating summer, RX and TX clocking, LOS detector)* Interactions with multiple BU units (technical and schedule) and senior management* Revision A prototyping in progress. Revision B (bug fixes, performance optimization, and power reduction) in progress.Trained other Microchip Technology divisions on designing in 28nm process and specialized analysis flows (electromigration, electrical overstress, aging/self-heating)Consultant for 6ff infrastructure development and process node bring-upArchitecture consultant for feasibility work on PAM4 SERDES subsystems development in 6ff

San Jose, California, Us

Development of 16ff test structures chip for assessing matching characteristics of resistor and MOS arrays and ESD TLP structures* Included design, testing/characterization, and preparation of characterization reportAnalog technical lead for 10G GPON/EPON OLT SERDES development in 28nm* Included 3.3V-tolerant burst-mode receiver IO and ESD protectionDeveloped ESD protection process flow and training materials for High Performance PHY groupLead ESD protection consultant for USB/PCIe SERDES macro in 10ff process. * Included ESD planning for IP macros, characterization of ESD library protection elements* Direct interfacing with lead customer and fab for ESD reviews.Feasibility/architecture work for 28Gb/s half-rate serializer and voltage-mode transmitter in 16ffc Designed CCIX-25G/10G-KR half-rate serializer and voltage mode transmitter in 7ff

Us

Led working group on 28nm technology infrastructure bring-upTechnical lead for general purpose and high-performance standard cell libraries and SERDES component reuse library in 28nmAnalog lead for 12G SAS/6G SATA/PCIe Gen 3 SERDES in 28nmESD protection consulting for SERDES designs (various process nodes)

Us

Feasibility/architecture for high-swing (1.8Vpp) voltage mode transmitter for SAS2 in 40nmDesigned PFD, CP, VCO, and complete PLL for PCIe Gen 3/2/1 applications in 40nmDesigned serializer and voltage mode transmitter for 10.3125 Gb/s GPON/EPON in 40nm. * IP served as reference design for other developments (12Gb/s SAS, 12.5 Gb/s OTN)Architect and analog lead for transmit line-side SERDES for 40G OTN applications in 40nm* Interactions with internal BU units (technical + schedule) and with lead customer (technical)

Us

Designed 6 GHz clock phase generator IP using actively-peaked CML in 0.13umContributed to 3Gb/s SAS/SATA CML transmitter design in 0.13umDesigned 3Gb/s SAS/SATA voltage mode transmitter in 0.13um. * Included novel (patented) architecture for efficient FIR EQDesigner for top-level macro of dual-band 802.11 radio chip in 0.18um. * Included an aggregation of baseband processing, up/down converters, LNA, and pre-PA, JC-61 interface and full padringDesigned tri-band up-converters (2G, 3G, 5G carriers) for 802.16e radio chip in 0.18umDesigner for DCRU subsystem and co-analog lead for single-channel GPON loop-timed ONU SERDES (1.244Gb/s transmit, 2.488Gb/s receive) in 90nm

Montreal, Qc, Ca

Taught undergraduate introductory course in microelectronic circuits.

London, Gb

Designed transmitter/receiver circuits for large-scale free-space optoelectronic-VLSI ASIC.

Ca

Designed, tested, and characterized Gb/s point-to-point discrete free-space optical interconnects.

Redmond, Washington, Us

Four month internship in program management group (Microsoft Word).

Ph.D, Electrical Engineering

M.Eng., Electrical Engineering

Bachelor Of Engineering - B.Eng., Electrical Engineering

Dec, Pure And Applied Science

High School Diploma