Michael Wang Email & Phone Number

EDUCATION:2001–2003​National Sun Yat-Sen University Master of Science -ElectricalEngineering Professional Scope:​Product Yield ramp up at TSMC and R&D at ASE (Total ~22 years)● Over 2 years’ experience in assembly house (ASE) of bumping and flip chip in engineering development.● Around 20 years’ experience in wafer fabrication (TSMC):1. CP yield improvement of N28(HKMG); N16(3D FinFET); N5(EUV process) products.2. Systematic failure mode definition and solving.3. Wafer fabrication Integration process improvement.4. Quality & Reliability monitor and control.5. EFA / PFA failure analysis skill (SEM/ TEM/ FIB/ EDS/ nanoprobing) in product yield analysis department.6. NTO (Layout study / FA analysis/ Yield break through).7. Good communication and interpersonal skills8. Patient, fast worker, positive attitude9. Work effectively under high pressure.WORK EXPERIENCE:May 2003 – TSMC Ltd.à Advanced Product Manager: Product Engineering Department ● Major Job scope:1. Business Impact: (1) D0 reduction rapidly, (2) Critical product device targeting definition, (3) Quickly solving large yield loss in each product initial stage.2. Cross Organization Contribution: (1) Co-work with customer to handle major yield loss issues smoothly. To minimize the risk of both companies. (2) Key customer 1st Pilot lots yield Goal achievement.3. People Development: (1) Well build up my leaders (2) Enhance technical depth of team members. ● TSMC Key Contribution Cases:1. Case I: Customer Systematic for high volume product for 5nm: (1) Rapidly identify failure mechanism for unique layout, (2) Cowork with customer to improve their design, (3) Action: Implement the design rule to prevent same issue happening again.2. Case II: Customer 1st key product ramping low yield for 28nm: (1) Tool & PFA analysis to identify failure mode, (2) Root cause for bad Tool impacted, (3) Action: separate issued tool grouping to fix this event.3. Case III: RF product Mother Fab transfer yield break through from 0% to 94%: (1) RF 1000X high leak solved, (2) NLDD missing by process improvement, (3) Fab BKM/CIP for yield improvement by PFA Pareto. WORK EXPERIENCE:Aug. 1998 – Aug. 2001 ASE Ltd.àAdvanced R&D Engineer: Research & Development Department ● ASE Key Contribution Cases:1. Responsible of advanced CPU/GPU products technology stability with flip-chip bump process.2. Improved low yield issues by new process package (Film BGA, MCM…) and quality stability control.3. Achievement with key Qual project & Engineering study by customers requirement

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  Manager

  Tsmc

  May 2003 - Present - 台灣

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  國立中山大學

  半導體固態電子 電機/電子研究所