Michael Meyer

Michael Meyer Email and Phone Number

Principal Engineer at D2S, Inc. @ D2S, Inc.
Michael Meyer's Location
Palo Alto, California, United States, United States
Michael Meyer's Contact Details

Michael Meyer personal email

n/a
About Michael Meyer

I have more than 30 years of experience leading and developing EDA and IP products combining a deep knowledge of hardware and software and with a passion for delivering a high quality product. I'm applying deep learning to problems in electronics manufacturingSpecialties: EDA tools and methodologies, especially high-level synthesis, SOC modeling and EDA databases. Software for semiconductor manufacturing. System Architecture, especially interconnect and DRAM performance. Deep Learning.Languages: Python (including NumPy, Pandas and TensorFlow), MATLAB, C++, C, CUDA, Verilog, SystemC, & Skill.

Michael Meyer's Current Company Details
D2S, Inc.

D2S, Inc.

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Principal Engineer at D2S, Inc.
Michael Meyer Work Experience Details
  • D2S, Inc.
    Principal Engineer
    D2S, Inc. Jan 2023 - Present
    San Jose, California, Us
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  • D2S, Inc.
    Vp Of Engineering, Truemask(R) Products
    D2S, Inc. Feb 2020 - Jan 2023
    San Jose, California, Us
    View
  • Center For Deep Learning In Electronics Manufacturing (Cdle)
    Principal
    Center For Deep Learning In Electronics Manufacturing (Cdle) Oct 2018 - Jan 2020
    Helping member companies apply deep learning in electronics manufacturing.
  • D2S, Inc.
    Principal, Deep Learning
    D2S, Inc. Mar 2018 - Sep 2018
    Applying Deep Learning to semiconductor manufacturing.
  • Self-Employed
    Exploring New Areas
    Self-Employed May 2017 - Feb 2018
  • Cadence Design Systems
    Fellow - Ipg (Cto/Systems & Software)
    Cadence Design Systems Jan 2016 - Apr 2017
    San Jose, California, Us
    Led team developing high-level DDR subsystem models and performance analysis tools.Managed teams doing neural network optimization and vision for automotive applications.
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  • Cadence Design Systems
    Fellow - Ipg Vip
    Cadence Design Systems Dec 2014 - Dec 2015
    San Jose, California, Us
    PCIE TL Verfication.Investigated extending VIP-based verification to include device drivers and software stack.
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  • Cadence Design Systems
    Fellow - System Level Design (Sld)
    Cadence Design Systems Apr 2010 - Nov 2014
    San Jose, California, Us
    Technical lead for CtoS, Cadence's high-level synthesis tool.
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  • Cadence Design Systems
    Vp R&D - C-To-Silicon
    Cadence Design Systems May 2005 - Apr 2010
    San Jose, California, Us
    Responsible for the development of Cadence C-to-Silicon Compiler, a high-level synthesis tool that generates high quality synthesizable RTL from a SystemC program. Led the development of this new product from prototype to production release.
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  • Consultant
    Jan 2005 - May 2005
    EDA consulting for companies using OpenAccess
  • Sonics, Inc.
    Vp Of Engineering
    Sonics, Inc. Mar 2001 - Nov 2004
    San Jose, Ca, Us
    Responsible for the development of Smart IP including SiliconBackplane, MemMax, s3220, and SMX.
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  • Sonics, Inc.
    Director Of Software Development
    Sonics, Inc. Nov 1998 - Mar 2001
    San Jose, Ca, Us
    Responisible for the definition and development of the tool environment to support Sonics' configurable IP.
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  • Cadence
    Fellow
    Cadence 1995 - 1998
    San Jose, California, Us
    Worked with development and service organizations within Cadence to develop new SOC design methodologies. Was part of the group at Cadence that launched VSIA and worked as part of the OCB-WG group that developed the VCI specification.
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  • Cadence
    Chief Arhitect
    Cadence 1995 - 1998
    San Jose, California, Us
    Responisble for developing strategy and technology for integrating EDA tools from acquired companies.
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  • Cadence
    Framework Architect
    Cadence 1991 - 1994
    San Jose, California, Us
    Resonsible for the technical aspects of the Design Framework II development and use by internal tool groups as well as use by key customers.
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  • Cadence
    Sr. Manager
    Cadence 1988 - 1991
    San Jose, California, Us
    Manager of the group developing SDA's (which merged with ECAD to form Cadence) database CDBA and associated translators.
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  • Sda Systems
    Member Of Technical Staff
    Sda Systems Oct 1984 - 1988
    Developed tools for PLA design and optimization.As part of the technical marketing team, I worked with early customers to develop a specification for major improvements to the layout editor. I later transfered back to R&D and implemented the layout editor functionality and speed improvments.Also worked on the next generation database design and chaired the CFI database working group.
  • At&T Bell Laboratories
    Member Of Technical Staff
    At&T Bell Laboratories Feb 1980 - Oct 1984
    Dallas, Tx, Us
    Developed and integrated PLA design tools used in the BELLMAC32 microprocessor design. Also involved in C modeling of different supporting chips.
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Michael Meyer Skills

Eda Verilog C Soc C++ Asic Systemc Semiconductors Python Logic Synthesis Microprocessors Algorithms Embedded Systems Tcl Ic Integrated Circuit Design Debugging Rtl Design Perl System Architecture System On A Chip Software Engineering Software Development

Michael Meyer Education Details

  • Carnegie Mellon University
    Carnegie Mellon University
    Electrical Engineering
  • University Of Nebraska-Lincoln
    University Of Nebraska-Lincoln
    Computer Science

Frequently Asked Questions about Michael Meyer

What company does Michael Meyer work for?

Michael Meyer works for D2s, Inc.

What is Michael Meyer's role at the current company?

Michael Meyer's current role is Principal Engineer at D2S, Inc..

What is Michael Meyer's email address?

Michael Meyer's email address is m_****@****ell.net

What schools did Michael Meyer attend?

Michael Meyer attended Carnegie Mellon University, University Of Nebraska-Lincoln.

What skills is Michael Meyer known for?

Michael Meyer has skills like Eda, Verilog, C, Soc, C++, Asic, Systemc, Semiconductors, Python, Logic Synthesis, Microprocessors, Algorithms.

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