Principal Engineer
Current
Jan 2023 - Present
AeroLeads people directory · profile
Michael Meyer Email & Phone Number
Principal Engineer at D2S, Inc.
at
D2S, Inc.
1 work email found
@pacbell.net
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
Principal Engineer at D2S, Inc.
Location
Palo Alto, California, United States
Who is Michael Meyer? Overview
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Quick answer
Michael Meyer is listed as Principal Engineer at D2S, Inc. at D2S, Inc., based in Palo Alto, California, United States. AeroLeads shows a work email signal at pacbell.net and a matched LinkedIn profile for Michael Meyer.
Michael Meyer previously worked as Principal Engineer at D2S, Inc. and VP of Engineering, TrueMask(R) products at D2S, Inc.. Michael Meyer holds Ms, Electrical Engineering from Carnegie Mellon University.
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Email format at D2S, Inc.
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{first_initial}{last}@pacbell.net
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Profile bio
About Michael Meyer
I have more than 30 years of experience leading and developing EDA and IP products combining a deep knowledge of hardware and software and with a passion for delivering a high quality product. I'm applying deep learning to problems in electronics manufacturingSpecialties: EDA tools and methodologies, especially high-level synthesis, SOC modeling and EDA databases. Software for semiconductor manufacturing. System Architecture, especially interconnect and DRAM performance. Deep Learning.Languages: Python (including NumPy, Pandas and TensorFlow), MATLAB, C++, C, CUDA, Verilog, SystemC, & Skill.
Listed skills include Eda, Verilog, C, Soc, and 19 others.
Current workplace
Michael Meyer's current company
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18 roles · 38 years
Michael Meyer work experience
A career timeline built from the work history available for this profile.
Vp Of Engineering, Truemask(R) Products
Feb 2020 - Jan 2023
Principal
Center For Deep Learning In Electronics Manufacturing (Cdle)
Helping member companies apply deep learning in electronics manufacturing.
Oct 2018 - Jan 2020
Principal, Deep Learning
D2S, Inc.
Applying Deep Learning to semiconductor manufacturing.
Mar 2018 - Sep 2018
Exploring New Areas
Self-Employed
May 2017 - Feb 2018
Fellow - Ipg (Cto/Systems & Software)
Led team developing high-level DDR subsystem models and performance analysis tools.Managed teams doing neural network optimization and vision for automotive applications.
Jan 2016 - Apr 2017
Fellow - Ipg Vip
PCIE TL Verfication.Investigated extending VIP-based verification to include device drivers and software stack.
Dec 2014 - Dec 2015
Fellow - System Level Design (Sld)
Technical lead for CtoS, Cadence's high-level synthesis tool.
Apr 2010 - Nov 2014
Vp R&D - C-To-Silicon
Responsible for the development of Cadence C-to-Silicon Compiler, a high-level synthesis tool that generates high quality synthesizable RTL from a SystemC program. Led the development of this new product from prototype to production release.
May 2005 - Apr 2010
Consultant
EDA consulting for companies using OpenAccess
Jan 2005 - May 2005
Vp Of Engineering
Responsible for the development of Smart IP including SiliconBackplane, MemMax, s3220, and SMX.
Mar 2001 - Nov 2004
Director Of Software Development
Responisible for the definition and development of the tool environment to support Sonics' configurable IP.
Nov 1998 - Mar 2001
Fellow
Worked with development and service organizations within Cadence to develop new SOC design methodologies. Was part of the group at Cadence that launched VSIA and worked as part of the OCB-WG group that developed the VCI specification.
1995 - 1998
~3 yrs
Chief Arhitect
Responisble for developing strategy and technology for integrating EDA tools from acquired companies.
1995 - 1998
~3 yrs
Framework Architect
Resonsible for the technical aspects of the Design Framework II development and use by internal tool groups as well as use by key customers.
1991 - 1994
~3 yrs
Sr. Manager
Manager of the group developing SDA's (which merged with ECAD to form Cadence) database CDBA and associated translators.
1988 - 1991
~3 yrs
Member Of Technical Staff
Sda Systems
Developed tools for PLA design and optimization.As part of the technical marketing team, I worked with early customers to develop a specification for major improvements to the layout editor. I later transfered back to R&D and implemented the layout editor functionality and speed improvments.Also worked on the next generation database design and chaired the.
Oct 1984 - 1988
Member Of Technical Staff
Developed and integrated PLA design tools used in the BELLMAC32 microprocessor design. Also involved in C modeling of different supporting chips.
Feb 1980 - Oct 1984
2 education records
Michael Meyer education
Ms, Electrical Engineering
Carnegie Mellon University
Bs, Computer Science
University Of Nebraska-Lincoln
FAQ
Frequently asked questions about Michael Meyer
Quick answers generated from the profile data available on this page.
What company does Michael Meyer work for?
Michael Meyer works for D2S, Inc..
What is Michael Meyer's role at D2S, Inc.?
Michael Meyer is listed as Principal Engineer at D2S, Inc. at D2S, Inc..
What is Michael Meyer's email address?
AeroLeads has found 1 work email signal at @pacbell.net for Michael Meyer at D2S, Inc..
Where is Michael Meyer based?
Michael Meyer is based in Palo Alto, California, United States while working with D2S, Inc..
What companies has Michael Meyer worked for?
Michael Meyer has worked for D2S, Inc., Center For Deep Learning In Electronics Manufacturing (Cdle), Self-Employed, Cadence Design Systems, and Sonics, Inc..
How can I contact Michael Meyer?
You can use AeroLeads to view verified contact signals for Michael Meyer at D2S, Inc., including work email, phone, and LinkedIn data when available.
What schools did Michael Meyer attend?
Michael Meyer holds Ms, Electrical Engineering from Carnegie Mellon University.
What skills is Michael Meyer known for?
Michael Meyer is listed with skills including Eda, Verilog, C, Soc, C++, Asic, Systemc, and Semiconductors.
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