As a member of the architecture team researching the next generation of binary translation processors, I owned the host instruction set architecture and associated documentation and infrastructure. I worked directly with other hardware and software architects to define new features especially in regard to their feasibility and impact at the instruction, register and exception level. The complete ISA was implemented in C reference code and compiled as part of the functional simulator which was used to run an advanced binary translation software. I coordinated with software, microarchtects, simulation engineers and validation engineers to define, implement and test features on an ongoing basis.

Managed team of design engineers responsible for delivering the company's next generation PCIe 3 switch. Managed the project from microarchiecture through tapeout. Led the 'tiger team' debug effort to diagnose and resolve problems with custom multiport memory IP. Managed effort to diagnose, debug, FIB and tapeout PCIe/PCI-X bridge. Recruited, hired and trained new design team. Supported validation, sustaining and timing closure efforts for various projects.

Managed team of CPU logic designers working with architecture, physical design, DFT and test teams to define the microarchitecture of the next generation microprocessor. Planned, scheduled, completed and reviewed specifications for major blocks including front end, memory pipe and floating point units. Generated various proposals as part of partnership with Sony Corporation on Cell microprocessor. Managed functional verification of test chips. Managed group of verification engineers from mid to late project through completion of test plans and regression effort.

Microarchitecture, design, specification, implementation, timing analysis, verification and debug. Floating point and 2D graphics.

Microarchitecture, design, specification, implementation, synthesis and timing of 3D graphics ASIC. PCB placement, schematic entry and PAL programming for video workstation. Lab setup and support. Diagnosed manufacturing defects and fallout.