Mickey Geftler Email & Phone Number

Israel

Principle DFT engineer developing complex reticle size ASIC.Directed and executed the full DFT implementation for a high-speed networking SOC, indicating the presence of over 45 unique blocks, employing a hierarchical multi-mode ATPG architecture.▣ Developed and enhanced the ATPG flow for robustness and future scalability, incorporating deep coverage analysis.▣ Effectively managed third-party IP integration from a DFT perspective, optimizing ATPG and adeptly resolving integration challenges.▣ Led the definition of power-oriented pattern generation flow to optimize scan pattern efficiency and optimize power consumption in equal cooperation with BE team.▣ Delivered comprehensive DFT training to design teams, extending DFT knowledge across the organization.▣ Conducted gate-level simulations to expedite execution.▣ Defined a hierarchical SDF (timing) simulation flow for hierarchical blocks.▣ Built and led a multinational DFT team (8 members), overseeing critical tasks such as DRC cleaning, ATPG block-level runs, pattern generation, and pattern coverage debugging.▣ Pioneered the development of a robust, configurable, and fully automatic DFT flow environment, complete with a real-time status web interface.▣ Defined a scalable and robust memory BIST (SMS) architecture, ensuring its area, test time and power efficiency.

Haifa Area, Israel

Played a DFT pivotal role in an Automotive ADAS SOC project, making significant contributions to the design of an SOC with over 93% of the area dedicated to memories.▣ Specialized in automotive-grade MBIST (Memory Built-In Self-Test) architecture to ensure the reliability and functionality of critical memory components.▣ Defined and implemented Memory power management IP, collaborating closely with the global DFT team to optimize memory testing and power consumption in the context of automotive safety standards.

Haifa Area, Israel

▣ Modeled and integrated multi-power domain flows in prototype design, including third-party Ips.▣ Optimized RTL integration in HAPS 80 for FPGA prototyping, improving prototype performance.

Haifa Area, Israel

Scan designerImplemented SCAN as part of the Test-Fabric architecture and conducted parallel/serial pattern simulations during pre-silicon processes.

Israel

▣ Designed and implemented automotive-grade DFT architecture.▣ Performed deep coverage loss analysis and improved pattern efficiency.▣ Collaborated on third-party IPs integration and IP DFT improvements.▣ Generated production patterns and conducted post-silicon failure analysis.▣ Led the entire Tessent ATPG flow development, resulting in the creation of high-performance production patterns for a limited volume.

▣ Contributed to micro-architecture development and RTL Verilog implementation for ASIC SD/MMC controllers.▣ Implemented memory High-Speed Serial Interface protocols, handled multiple clock domain designs, and engaged in RTL design and GL simulations.▣ Created a system for injecting errors into the SD protocol, starting from the definition and proceeding all the way to FPGA implementation.

Planned and designed custom standard cell libraries for automatic P&R tools.Characterized standard cells and managed full chip/macro P&R, including top-level layout verification.

Master Of Science - Ms, Electrical Engineering And Management, A

(Uncompleted thesis work). • Thesis Topic: Power Efficient Arithmetics in Image Processing pipelines.

Research Associate, Electrical Engineering Research

Research topic: “Methodology for the design of Continuous-Time Delta-Sigma modulators”. Research and proof of mathematical theory..

Bachelor Of Technology (B.Tech.), Electrical Engineering, 90 (A Us Scale)

Cum laud

Practical Engineer, Electronics, 90 (A Us Scale)

M.Sc., Electrical Engineering