Manager of the programmability team in the Packet processing group- Recruiting a team to build the next generation packet-processor HW and SW. - Definition of the HW architecture and micro architecture.- Definition of a language to describe the packet processor required functionality- Building a C++ based compiler to configure the HW

Research project to define the next-generation Packet processor - Definition of the HW architecture and micro architecture.- Definition of a language to describe the packet processor required functionality- Building a C++ based compiler to configure the HW

Packet processing group:- Micro architecture block definition, design in Verilog, basic synthesis.- Block level verification: Build environment in SystemVerilog, Test definition and execution.- Full chip verification.- Post silicon validation

Teaching assistant at the course "Introduction to computer networks" at the Electrical Engineering faculty in the Technion.

PTLi.sim department, infotainment group.A full time job during summer vacation.Building VOIP application in Linux environment as part of an infotainment software to lower the power consumption in laptops.

PTLi.sim department, proccesor groupA full time job during summer vacation.A research project to find new technologies for cpu simulations in order parallelize the run of the simulation

Arch department, performance group.Developing simulation tools and RTL validation for the Centrino project