Muhammad Ijaz Email & Phone Number

Barcelona, Catalonia, Spain

𝗘𝘂𝗿𝗼𝗽𝗲𝗮𝗻 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗜𝗻𝗶𝘁𝗶𝗮𝘁𝗶𝘃𝗲 (𝗘𝗣𝗜) & 𝗘𝗨𝗣𝗜𝗟𝗢𝗧 𝗣𝗿𝗼𝗷𝗲𝗰𝘁𝘀:• Enhanced RISC-V Vector Processing Unit (VPU): Integrated support for vector tail-agnostic policy, significantly boosting performance for vectorized operations• Optimized Mask Unit: Improved efficiency of vector mask instructions by optimizing the mask unit, enhancing overall execution• FPGA Collaboration: Worked closely with FPGA teams to optimize synthesis, reduce area, minimize LUT usage, and remove timing bottlenecks, ensuring a highly efficient implementationEPI: https://www.european-processor-initiative.eu/EUPILOT: https://eupilot.eu/𝗣𝗘𝗥𝗧𝗘 𝗖𝗵𝗶𝗽 𝗣𝗿𝗼𝗷𝗲𝗰𝘁:• Scalar-VPU Interface Refinement: Streamlined the handling of vector memory instructions, leading to notable performance improvements• Mask Unit Parameterization: Designed a scalable mask unit with a focus on 16-lane architectures, ensuring flexibility across lane configurations• Verification Collaboration: Partnered with verification teams to ensure the RTL design met all functional and performance goalsPERTE: https://commission.europa.eu/projects/perte-chip-strengthening-scientific-and-technological-ecosystem-increased-design-capabilities_en

Lahore, Punjab, Pakistan

• Worked on CVA6, a RISC-V application-class core developed at ETH Zurich and maintained by OpenHW Group. Added support for bit-manipulation extensions (Zba, Zbb, Zbc, Zbs)• Updated core-v-verif to integrate the latest riscv-arch-test suite, ensuring compliance with updated RISC-V standards• Contributed to the development of ARA, a RISC-V vector co-processor for CVA6, adding support for vector mask operations, permutations, and fixed-point arithmetic• Optimized load segment instructions for better memory access efficiency in vectorized workloads• Collaborated closely with teams from ETH Zurich and OpenHW Group for compliance and performance testing• Underwent an intensive and tailored training plan focused on advanced C programming, RISC-V assembly, Digital Logic Design, Verilog, System Verilog, and an in-depth understanding of cache memory types and virtual memory• Gained expertise in various aspects of computer architecture, equipping me with a strong foundation to tackle complex challenges• Successfully engineered a sophisticated five-stage pipelined RISC-V core based on the RV32I base instruction set• Demonstrated expertise in Verilog by designing and meticulously verifying an APB bus slave, skillfully implementing a finite state machine for efficient and reliable data transfer

Lahore, Punjab, Pakistan

• Completed a 6-week internship with a primary focus on understanding the working principles of modern water dispensers• Gained hands-on experience in the manufacturing processes associated with these dispensing systems• Acquired insights into the operational intricacies of state-of-the-art water dispenser technology

Lahore, Punjab, Pakistan

• Worked on generating an automated python web-scrapper in order to scrap the courses offered for BS and MS in all the public and private universities of Pakistan which fall under the recognition of Higher Education Commission of Pakistan (HEC)• Worked on generating the Design Layout of Mobile Application (Andriod and IOS) and Web-Page using Adobe-XD and Adobe Illustrator

Electrical Engineering (Specialization Computer Engineering)

Intermediate, Pre-Engineering

Matric, Science