Experienced RTL Design Engineer with over 3 years specializing in RISC-V architecture and VPU design. Skilled in Verilog and SystemVerilog, with a proven track record in developing high-performance and efficient hardware solutions.Currently focused on advancing open-source hardware projects, with a strong interest in GPU RTL design. Known for delivering robust, scalable designs and thriving in collaborative, innovative environments. Passionate about pushing the boundaries of processor and accelerator technologies to drive the next generation of digital systems.