Mike Li Email and Phone Number
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Engineering Leader for: - 1) Artificial Intelligence, Convolutional Neural Network based Deep Learning architecture, hardware accelerator architecture and computer arithmetic -2) Pioneering ASIC Design with 28/16nm/7nm CMOS technologies, on low power mixed signal chip design, IP strategy. -3) System On Chip (SoC), DSP, and Application Processor solutions to wireless base station and low power mobile handsets (WiFi, Bluetooth, GPS, 3G/WCDMA/TDS-CDMA) -4) FBAR/MEMS mixed signal IC, BiCMOS communications RFICRecent Achievements:- Drove the world’s first 16/7nm PAM4 400Gbps mixed signal DSP chip into production- Led the first commercial FBAR CMOS oscillator chip design, created Avago’s timing product line. - Contributed actively in the creation of Mobile Business Unit at Atheros Communications (acquired by Qualcomm) as SoC Architect.
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Vp Of Engineering And New ProductsCorigine 2021 - PresentSanta Clara, California, Us★ Engineering management for 6nm SmartNIC/DPU Chiplets:✧ Drove system and solution architecture for SmartNIC chiplets. Led architecture and micro architecture optimizations to achieve ultra low latency and scalability. Managed external fab relationship, led IP evaluation, customization esp. 112G PAM4 DSP Serdes and Die to Die IP. Initiated architecture optimization for ultra low latency applications. Initiated program management, training, tech forums for SW/HW engineering teams. Presented the company at AI Hardware Summit, Chiplet Summit, DAC etc. events.★ Managed Technical Marketing and Application Support of FPGA Product Line:✧ Started with consultation, eventually drove product differentiation and marketing strategy. Closed the first tier-1 design win and post sale support in North America. Helped grow emulator revenue multifold in two years.✧ Envisioned large scale FPGA based AI-cluster for Large Language Model neural networks training and inference in Data Centers, and initiated tier-1 partner cooperation -
Vice President Of EngineeringNovumind Inc. 2017 - 2021Santa Clara, California, Us• Drove architecture innovations for AI accelerators: ◦ Directly supervised the Algorithm & Architecture Team. Led computer vision and neural network research, convolutional neural network(CNN) processor unit (NPU) and SoC level architecture design, behavior and cycle accurate modeling. Authored multiple patents in improving CNN arithmetic efficiency and accuracy. Led innovations in spatial video up-sampling (Super Resolution) algorithm and hardware micro-architecture ◦ Executed solution architecture, technical marketing and support initiatives, formed industry alliance at CES, Embedded Vision Summit, DAC etc.. Achieved sales from major telecom operator and television maker. • Built multi-discipline engineering teams and achieved 1st-pass silicon and HW/SW systems: ◦ Managed RTL design/verification teams, synthesis/timing teams, & physical implementation service. Drove post silicon bring up and characterization across multiple vendor teams; ◦ Initiated the system architectures for edge server and camera system. Built and managed multi-site teams in development of PCB boards, driver and SDK system. Drove high speed circuit power integrity and signal integrity improvements and optimized power and cost efficiencies for production boards. -
Technical DirectorInphi Corporation 2014 - 2017San Jose, California, Us• Drove 16nm and 7nm FinFET technology evolution. Led vendor comparison, library and IP evaluation, power/performance/area analysis for mixed signal processing. Established company wide cross flow low power methodology. • Led the architecture and mixed signal circuit designs in 2 products of 400Gbps Pulse Amplitude Modulation (PAM4) Serializer/De-serializer(Serdes) SoC at FinFET node. Drove SoC and micro-architecture innovations in high speed SAR ADC, signal processing, on chip IP interconnect* Led design, integration, and implementation of a gigantic Serdes chip. This is part of a Silicon Photonics system with about 100 lanes of 28Gbps Ethernet Serdes on a monolithic die for a major networking equipment maker. -
Technical Director, Cmos EngineeringAvago Technologies 2011 - 2014San Jose, Ca, Us- Drove CMOS based digital and mixed signal design in the Wireless Semiconductor Division(WSD). Innovated signal processing and RF control/calibration solutions, Created digital on top and analog on top design flows. Created NI PXI based bench testing and probing platform.- As Chip Lead, Delivered world’s first femto second level ultra low jitter (fem to second RMS jitter) FBAR based reference clock source. - Started engineering team of designers and contractors, formed Timing Product Line in Avago WSD with tier-1 equipment vendor and optical networking design wins.
Mike Li Skills
Mike Li Education Details
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Stanford UniversityHigh Speed Adc Architecture -
New York University - Polytechnic School Of EngineeringElectrical Engineering -
University Of Electronic Science And Technology Of ChinaCommunications Engineering
Frequently Asked Questions about Mike Li
What company does Mike Li work for?
Mike Li works for Corigine
What is Mike Li's role at the current company?
Mike Li's current role is VP of Engineering, AI computing and data center communication.
What is Mike Li's email address?
Mike Li's email address is mi****@****ind.com
What is Mike Li's direct phone number?
Mike Li's direct phone number is +165071*****
What schools did Mike Li attend?
Mike Li attended Stanford University, New York University - Polytechnic School Of Engineering, University Of Electronic Science And Technology Of China.
What skills is Mike Li known for?
Mike Li has skills like Soc, Cmos, Arm, Mixed Signal, Digital Signal Processors, Integrated Circuit Design, Ic, Rf, Application Specific Integrated Circuits, System On A Chip, Integrated Circuits, Field Programmable Gate Arrays.
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