Mike Knapp Email & Phone Number

· Managed an engineering team of 8, focusing on optimizing battery life and system performance in collaboration with US based mobile customers.· Worked with customers to meet laptop/tablet battery life targets and launch designs with Ice Lake, Alder Lake, Meteor Lake, and Lunar Lake SoCs· Worked cross-organizationally within the company to solve system level power & performance issues related to various subsystems

· Led a team dedicated to reducing system standby power on the Skylake SoC reference design, achieving a system level reduction from 2W to 250mW· Worked with a key Skylake customer to troubleshoot and resolve power management issues, earning a Division Recognition Award for contributions.

· Led connected standby platform power optimization efforts to ensure that a key customer design based on Cherrytrail SoC met platform power targets. Worked directly with the customer to implement power management features and debug power issues specific to the platform.

· Designed a 40 channel power measurement solution that was deployed across the company to help teams optimize power for their subsystems, on a Haswell SoC based form factor reference design system. Developed Python scripts to screen and characterize the signal conditioning portion of the design to correct for DC offsets, and to program the gain of each current measurement channel.· Owned platform level power measurements for the Sandy Bridge CPU. Was responsible for ensuring that… Show more · Designed a 40 channel power measurement solution that was deployed across the company to help teams optimize power for their subsystems, on a Haswell SoC based form factor reference design system. Developed Python scripts to screen and characterize the signal conditioning portion of the design to correct for DC offsets, and to program the gain of each current measurement channel.· Owned platform level power measurements for the Sandy Bridge CPU. Was responsible for ensuring that components met pre-determined targets and delivering ratified Intel component power measurements to Marketing for customer collateral. Built relationships and worked with PCH (IO hub) and CPU power labs to identify and correct platform level power issues. Regularly provided platform power health updates to the Sandy Bridge program office. Identified, filed, and drove issue resolution on power-related sightings. Show less

· Defined the initial placement of the IO hub, CPU and DIMMs for the Nehalem CPU reference board. Did pinout and routing studies for breaking out DDR signals. Worked with signal integrity teams to define the routing guidelines and publish in customer collateral.· Was responsible for floor planning, schematics, and overseeing layout of a reference board for a new chipset. Chaired the electrical validation hooks working group to help EV board customers define the board feature set.·… Show more · Defined the initial placement of the IO hub, CPU and DIMMs for the Nehalem CPU reference board. Did pinout and routing studies for breaking out DDR signals. Worked with signal integrity teams to define the routing guidelines and publish in customer collateral.· Was responsible for floor planning, schematics, and overseeing layout of a reference board for a new chipset. Chaired the electrical validation hooks working group to help EV board customers define the board feature set.· Developed two boards for a test chip designed to verify functionality of new IO standards like DDR3 and CSI on new process technology. Defined the feature set, board stack up and geometry, floorplan, method for margining voltage regulators, and programmable power sequencing. Show less

· Led the PCB design for a dual display desktop concept system, which was meant to demonstrate the new dual display capabilities of an integrated graphics chipset. It was shown by execs at a keynote, at the Intel Developers Forum in San Jose.

· Designed a prototype PCB to investigate the impact of enabling mobile power saving features on a desktop board· Worked with third party vendors to develop a chip to control fan speed based on CPU and chassis air temperatures

· Developed C++ based automation to run compatibility validation on Intel based RAID controllers across a variety of operating systems· Ran Circuit Marginality Validation on a newly released chipset, automated testing of temperature and voltage