Mike Pak Email & Phone Number

San Jose, Ca, Us

Santa Clara, California, United States

Santa Clara, Ca

Project Manager – Delivered overall testable content for Intel’s Advanced Non-volatile Memory Technology- Coordinated efforts of 30+ engineers spanning multiple departments- Managed schedule, operations, logistics and deliverables of sub-teams and individuals- Monitored project progress and updated status to upper management on expected completion timeline.- Mentored fellow colleagues and new hires on my technical area of expertise.

Santa Clara, California, United States

Business Co-Owner- Planned and strategized revenue growth plan and differentiated service offerings.- Managed capital allocations for business- Provided accounting and IT related support.

San Jose, California, United States

Taught a class consist of 46 students on topic of operation management:o Project Managemento Product Design and Serviceso Operation Strategyo Supply Chain ManagementIllustrated operation concepts through real case-study and examples from personal work experience, and mentored students for their potential career path

San Jose

Staff Engineer – Overall Testable Content and Design of Experiment (DOE) Owner for Tapeoutfor leading edge Process Nodes and Memory Technology Tapeouts. Interfaced, and Negotiatedintricate logistics with various Clients, and coordinated design efforts from multiple designteams across the Globe.- 7nm and 14nm Logic Process Characterization Vehicle Tapeout and Project Managemento New Test Structure and Testing Methodology Development to monitor CriticalProcess Integration FailModeso Explore Test Structures based on IP based patternso Design Rule Validations for Cliento Managing Communications and Setting Expectations to Client and Internal Team interms of deliverables and meeting scheduled milestones- 28nm NVM Memory Test Vehicle Tapeout and Project Managemento Conceptualize and Design of new Test Structure Integration SpecificFailmodes, and process monitor o Innovative Ways to route and Test Memory Cell for Short Loop Flowo Coordinating Efforts of multiple design team across different sites

San Francisco Bay Area

San Francisco Bay Area

Sr. Device and Product Engineer – investigated, and segmented technology and yield issues for 45nm NOR Flash product through etest and sort parametric data analysis, statistical data trending, design/layout review and identified solution path to fix product and process issues.• Identified and root-caused critical sort bin, etest failures and defined solution path.• Delivered product leakage modeling that relates to device building blocks thus giving better visibility of failing components.• Developed and designed innovative test devices to monitor the process and yield issues • Delivered device characterizations for design process file library.• Identified Tester Hardware conversion path to 300mm wafer testing.• Transferred electrical test device architecture, their measurement methodologies and enabled production test monitoring in external foundary fab.

Component Design and Test Project Leader - Managed a small team of engineers and mask designers to deliver 65nm, and 45nm NOR Flash testchips and scribeline test devices to understand and improve layout, process, device and yield issues• Developed, Designed, and Debugged innovative functional blocks such as Flash miniarray, Big Flash Cells, BE testchips as well as other innovative test devices that monitors 45nm SAC process architecture thus providing valuable informations on fab processing health• Delivered innovative VT algorithms that provided 80% more stable VT readings for flash cells subject to Random Telegraph Noise fluctuations thus providing more stable ways to gauge the product read window budget• Developed and designed gate-oxide charge protection circuit which protected gate oxide from harmful plasma charge damaging thus reducing the defective fall outs by over 95%• Developed more efficient test packages that reduced test time by 30% while maintaining the integrity of test data

Component Design and Test Engineer - designed and tested 180nm, 130nm, and 90nm NOR Flash testchips and scribeline test devices to understand and improve layout, process, device and yield issues• Extensively characterized device components and building blocks such as Flash Cells, SRAM cells, CMOS transistors, special capacitors and resistors.• Defined, Designed and developed layout for Testchip and Scribeline process monitoring devices for 90nm and 130nm NOR Flash Technology.• Produced and standardized test program packages for automated tester used in production environment• Qualified and transferred and test deliverables to internal manufacturing fabs

Executive Mba Candidate

Master Of Science, Electrical Engineering

Bachelor Of Science, Electrical Engineering