Mikel Miller Email & Phone Number

Cupertino, California, Us

• Materials development, characterization, selection and targeted problem solving for Mac, iPhone, iPad SoC packaging• Underfill, EMC, TIM, lid, adhesive, stiffener, substrate, PCB/MLB, solder resist characterization• Modulus, CTE, strength, elongation, moisture absorption/swelling, cure kinetics, roughness & adhesion tests• InFO, DRAM, NAND and SIP package strength and SoC die strength studies• Reliability testing (TC, TH, HAST, multi-reflow) of materials, test coupons and SoC packaging• Lab Management - Packaging Materials & Mechanics Lab - Execution of lab move / expansion in 2021, plus daily operations - equipment purchasing, installation, maintenance, calibration, operation and training.

Darmstadt, De

• Material & process development of Transient Liquid Phase Sintering (TLPS) solder paste for power packages• Lab Manager – equipment upkeep, daily operations, workflow and activities of 2 technicians• Ramped up new Applications Lab with stencil printing, inspection, pick/place, reflow, X-Ray and die shear equipment, including installation, training, operation, qualification and documentation of procedures• Designed, fabricated and standardized test-vehicle PCBs and leadframes and sourced SMT components to develop process windows for TLPS solder paste formulations and assess quality & reliability risks• Developed Application Guidelines and Data Packages for TLPS solder paste formulations, then worked with Sales and Marketing team to officially publish them for customer use• Led effort to ensure process and data matching between labs in San Diego and Taiwan

Cambridge, Ma, Us

• Molded wafer, heterogeneous integration, redistribution layer (RDL) & through-mold-via (TMV) development in support of Draper’s iUHD 2.5D/3D fan-out wafer level packaging (FOWLP) technology,• Researched, sourced and characterized mold compound materials for next-generation molded wafer• Characterized effect of cure % on mechanical properties of mold compound and RDL dielectric material to minimize die-shift and warpage/stress throughout molded wafer process• Supported various IC packaging projects as tool owner/operator of K&S ICONN automatic Cu wirebonder• Led 2 projects with Assembly/Test subcontractor to post-process iUHD packages (die stack, wirebond, overmold, bump) and troubleshoot yield issues• Led task to define, test & select heat spreader, thermal interface material (TIM) and lid adhesive material for stacked iUHD package application. Once qualified, defined and implemented assembly process into low volume production.

Dallas, Tx, Us

• Improved mold compound and die attach adhesion to various leadframe finishes through supplier interactions and in-house adhesion testing at time-zero, after moisture exposure and other conditions• Empirically correlated adhesion data with finite element modeling and package qualification results to predict leadframe delamination risk for several future package configurations (ECTC ’11 paper)• Designed and fabricated test structures under bondpads, then probed, bonded, packaged and reliability tested those structures to challenge legacy Silicon design rules. Results enabled routing under bondpads, die shrink and increased die per wafer

Santa Clara, California, Us

• Performed package fault isolation and failure analysis (FI/FA) for several packaging development programs (flip-chip and wirebond) while working with and managing a Senior FA technician• Used metallography, microscopy, CSAM, X-Ray, FIB, SEM/EDS, XPS, Tof-SIMS as tools to drive to root cause• Characterized intermetallic (IMC) type, growth rates and failure mechanisms in support of solder thermal interface material (Solder TIM) development for flip-chip CPU packaging• Developed, built and qualified first-in-industry Laser Spallation adhesion metrology, which converts laser pulses into stress pulses, to test adhesion of bumped die and integrated packages (ECTC ’02 paper)• Assessed chip-package interaction (CPI) issues by tracking wafer lots of SRAM test vehicle die through sort-test and subsequent builds into flip-chip assembly lots. Then tracked fallout through reliability testing and coordinated FI/FA to drive to root cause.

Ph.D., Materials Science & Engineering

M.S., Materials Science & Engineering

B.S., Materials Engineering, Cum Laude

Diploma