Mikel Miller

Mikel Miller Email and Phone Number

IC Packaging Engineer at Apple @ Apple
Mikel Miller's Location
Cupertino, California, United States, United States
Mikel Miller's Contact Details

Mikel Miller personal email

n/a

Mikel Miller phone numbers

About Mikel Miller

• IC packaging development & characterization (2.5D/3D, FOWLP, SiP, FCBGA & WB packaging) w/Q&R focus• Materials development/selection/testing, adhesion and reliability testing, failure analysis & metrology development• Lab setup/management, equipment qualification/operation/documentation, DOE and data collection/analysis• Working with suppliers, subcontractors and outside assembly/test facilities to achieve objectives• Mentoring and training junior/mid-level engineers, technicians and interns• B.S./M.S./Ph.D in Materials Science & Engineering with semiconductor packaging focus

Mikel Miller's Current Company Details
Apple

Apple

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IC Packaging Engineer at Apple
Mikel Miller Work Experience Details
  • Apple
    Ic Packaging Engineer
    Apple Jan 2020 - Present
    Cupertino, California, Us
    • Materials development, characterization, selection and targeted problem solving for Mac, iPhone, iPad SoC packaging• Underfill, EMC, TIM, lid, adhesive, stiffener, substrate, PCB/MLB, solder resist characterization• Modulus, CTE, strength, elongation, moisture absorption/swelling, cure kinetics, roughness & adhesion tests• InFO, DRAM, NAND and SIP package strength and SoC die strength studies• Reliability testing (TC, TH, HAST, multi-reflow) of materials, test coupons and SoC packaging• Lab Management - Packaging Materials & Mechanics Lab - Execution of lab move / expansion in 2021, plus daily operations - equipment purchasing, installation, maintenance, calibration, operation and training.
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  • Merck Group
    Principal Applications Engineer - Ormet Circuits / Emd Performance Materials
    Merck Group Jul 2017 - Jan 2020
    Darmstadt, De
    • Material & process development of Transient Liquid Phase Sintering (TLPS) solder paste for power packages• Lab Manager – equipment upkeep, daily operations, workflow and activities of 2 technicians• Ramped up new Applications Lab with stencil printing, inspection, pick/place, reflow, X-Ray and die shear equipment, including installation, training, operation, qualification and documentation of procedures• Designed, fabricated and standardized test-vehicle PCBs and leadframes and sourced SMT components to develop process windows for TLPS solder paste formulations and assess quality & reliability risks• Developed Application Guidelines and Data Packages for TLPS solder paste formulations, then worked with Sales and Marketing team to officially publish them for customer use• Led effort to ensure process and data matching between labs in San Diego and Taiwan
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  • Draper Laboratory
    Senior Member Technical Staff
    Draper Laboratory Jan 2011 - Jul 2017
    Cambridge, Ma, Us
    • Molded wafer, heterogeneous integration, redistribution layer (RDL) & through-mold-via (TMV) development in support of Draper’s iUHD 2.5D/3D fan-out wafer level packaging (FOWLP) technology,• Researched, sourced and characterized mold compound materials for next-generation molded wafer• Characterized effect of cure % on mechanical properties of mold compound and RDL dielectric material to minimize die-shift and warpage/stress throughout molded wafer process• Supported various IC packaging projects as tool owner/operator of K&S ICONN automatic Cu wirebonder• Led 2 projects with Assembly/Test subcontractor to post-process iUHD packages (die stack, wirebond, overmold, bump) and troubleshoot yield issues• Led task to define, test & select heat spreader, thermal interface material (TIM) and lid adhesive material for stacked iUHD package application. Once qualified, defined and implemented assembly process into low volume production.
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  • Texas Instruments
    Member, Group Technical Staff / Packaging Engineer
    Texas Instruments Nov 2005 - Jan 2011
    Dallas, Tx, Us
    • Improved mold compound and die attach adhesion to various leadframe finishes through supplier interactions and in-house adhesion testing at time-zero, after moisture exposure and other conditions• Empirically correlated adhesion data with finite element modeling and package qualification results to predict leadframe delamination risk for several future package configurations (ECTC ’11 paper)• Designed and fabricated test structures under bondpads, then probed, bonded, packaged and reliability tested those structures to challenge legacy Silicon design rules. Results enabled routing under bondpads, die shrink and increased die per wafer
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  • Intel Corporation
    Sr. Quality, Reliability And Failure Analysis Engineer
    Intel Corporation Sep 2000 - Oct 2005
    Santa Clara, California, Us
    • Performed package fault isolation and failure analysis (FI/FA) for several packaging development programs (flip-chip and wirebond) while working with and managing a Senior FA technician• Used metallography, microscopy, CSAM, X-Ray, FIB, SEM/EDS, XPS, Tof-SIMS as tools to drive to root cause• Characterized intermetallic (IMC) type, growth rates and failure mechanisms in support of solder thermal interface material (Solder TIM) development for flip-chip CPU packaging• Developed, built and qualified first-in-industry Laser Spallation adhesion metrology, which converts laser pulses into stress pulses, to test adhesion of bumped die and integrated packages (ECTC ’02 paper)• Assessed chip-package interaction (CPI) issues by tracking wafer lots of SRAM test vehicle die through sort-test and subsequent builds into flip-chip assembly lots. Then tracked fallout through reliability testing and coordinated FI/FA to drive to root cause.
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Mikel Miller Skills

Failure Analysis Semiconductors Materials Science Design Of Experiments Semiconductor Industry Electronics Materials Ic Mems Sensors Finite Element Analysis Testing Characterization Fmea Metrology Microelectronics Jmp Materials Analysis Cmos Manufacturing Reliability Engineering Risk Assessment Reliability Analysis Interferometry

Mikel Miller Education Details

  • The University Of Texas At Austin
    The University Of Texas At Austin
    Materials Science & Engineering
  • The University Of Texas At Austin
    The University Of Texas At Austin
    Materials Science & Engineering
  • Rensselaer Polytechnic Institute
    Rensselaer Polytechnic Institute
    Cum Laude
  • South Portland High School
    South Portland High School
    Diploma

Frequently Asked Questions about Mikel Miller

What company does Mikel Miller work for?

Mikel Miller works for Apple

What is Mikel Miller's role at the current company?

Mikel Miller's current role is IC Packaging Engineer at Apple.

What is Mikel Miller's email address?

Mikel Miller's email address is mi****@****mac.com

What is Mikel Miller's direct phone number?

Mikel Miller's direct phone number is +121440*****

What schools did Mikel Miller attend?

Mikel Miller attended The University Of Texas At Austin, The University Of Texas At Austin, Rensselaer Polytechnic Institute, South Portland High School.

What skills is Mikel Miller known for?

Mikel Miller has skills like Failure Analysis, Semiconductors, Materials Science, Design Of Experiments, Semiconductor Industry, Electronics, Materials, Ic, Mems, Sensors, Finite Element Analysis, Testing.

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