Michael Thomadakis Email & Phone Number

Houston, Tx, Us

San Ramon, Ca, Us

Analysis of emerging and next-gen HPC technologies as they apply to HPC and AI/DL workloads. Design and engineering of state-of-the-art HPC, AI/ML capability stacks for next-gen developer ecosystem.Innovative platform design for Oil and Gas applications. Performance analysis of HPC platforms. Architecture evaluation and design.Performance analysis and optimization of HPC and DL applications across alternative platforms.Cloud based HPC- Platform Evaluation- Workflow Design and Assesment

Sunnyvale, Ca, Us

* Development of performance analysis frameworks on accelerated HPC fabrics+ Analyzes application resource access usage patterns on the communications stack and explores ways to improve both.+ Carries out analysis and optimization of Oil & Gas related workloads, complex material sciences, Molecular-Dynamics and AI/ML applications on clusters.+ Optimizes the performance of HPC apps with alternative communications stacks (HPC_X, IntelMPI, MPT) on next generation HPC fabrics and different h/w platforms.+ Distributed memory, shared memory and accelerated parallel applications+ System-performance driven application optimization.* Performance Analysis of Next-Generation HPC h/w and s/w Communication Stacks+ Assesses the performance of new stack capabilities vs. communications patterns of complex HPC codes in science and engineering domains.+ Identifies new stack features that could improve the performance of applications based on dominant pattern.+ Investigates and tunes system performance at the different levels of the architecture (OMPI, UCX, HCOLL).+ Investigated and improved effectiveness and performance of NASA’s Pleiades dual-rail HPC fabric environment.* Bring-up of Next-Generation HPC h/w and s/w Communication Stacks Assists in the bring-up of next-generation fabrics in cutting-edge HPC clusters.+ Assisted IBM with troubleshooting the fabrics on Oak-Ridge National Lab’s Summit’s (ranked number one in Top500 in June 2018) and attain top performance and acceptance.+ Carried out computational experiments and tuned benchmarking for maximum Top500 performance of CPU and GPU partitions in first public next-generation HDR IB cluster.* HPC Technical Advocate+ Advocates application communications requirements to R&D.+ Advocates fabric system capabilities to application developers. Assists centers (NASA) and customers (HPE, ATOS) with utilizing effectively Mellanox accelerated communication stacks based on their applications.

London, England, Gb

Research and Development in High Performance Computing, Communications Systems and Parallel Applications- Researches, engineers and optimizes cutting-edge h/w and s/w technologies that substantially increase the computing and communications capabilities in R/D and production HPC systems.- Leads design and development of next generation H/W and S/W High-Performance Computing (HPC) environment integrating cutting-edge technologies, including, - Intel Phi (KNL, KNC) - HPC fabrics (Intel OmniPath, IB) - Nvidia GPUs (K20x, K80, P100) into state-of-the-art HPC clusters. - Engineers and optimizes complete HPC stacks from BIOS, OS, system S/W and application layers. Supports Nvidia GPU-Direct RDMA, programming environments for Intel MICs and HPC MPI communications. - Implementation of communication and computation system and user level S/W stacks for HPC clusters on MOFED and OPA. - Design and optimization of accelerator enabled parallel applications.- Performance analysis of GPU and co-processor enabled clusters and applications.- Performance, stability evaluation and optimization of OmniPath and IB stacks in HPC clusters.- Performance analysis and optimization of shared-memory, message-passing and accelerator enabled hybrid parallel applications.- Quantitative performance tuning for systems and applications based on platform's design and properties.- Performance Engineering of systems and parallel applications.

College Station, Tx, Us

* Mastering of Cutting Edge S/W and H/W technologies for High-Performance Computing (HPC) Systems and Applications* Performance Evaluation and Tuning of HPC Power5/AIX and Intel64/Linux based HPC clusters - CMP/Multi-Core Systems Evaluation for ccNUMA Effects - Multi-MPI stack performance evaluation (IntelMPI, OpenMPI, Mvapich2) - HPC Platform and GPU Benchmarking - OS and S/W stack tuning - Cache Coherence Protocol Evaluation* HPC Application Performance Evaluation and Tuning - Optimal Intra-Node Placement of Threads and Data - Impact of ccNUMA Effect on Applications - Bottleneck Discovery and Alleviation* Total HPC Systems Design for UNIX and Linux Clusters - IBM Power5+ 1600 Cluster with HPS and iDataPlex Intel64 cluster with QDR infiniband - OS and Networking tuning - Cluster High-Speed Interconnects tuning - High-Speed Storage* Assessment of cutting edge h/w and s/w technologies for HPC systems, including state of the art CISC and RISC micrarchitectures, SMP platforms, H/W accelerators and programming systems; * Instructional Resource Development for architecture-directed performance engineering of HPC applications * Complex Performance and Stability Problem Resolution at System and Application Level* Parallel and Distributed Algorithms* Alternative MPI stack tuning, S/W development stacks, Batch Schedulers* Assists complex HPC application development and tuning

College Station, Tx, Us

* Expanded research on Real-Time systems scheduling and design algorithms. - Hard Real-Time scheduling algorithms, optimal guaranteed aperiodic scheduling, formal analysis framework for optimal aperiodic scheduling algorithms - Optimal Soft Real-Time aperiodic scheduling under different scheduling disciplines* Re-developed from scratch and delivered graduate and undergraduate courses in the Computer Science Department. Updated the educational contents to align it with that in top tier Universities. - CPSC321 Computer Architecture, - CPSC612/463 Computer Networking and Distributed Processing - CPSC611/410 Operating Systems Design - CPSC603/310 Relational DBMS Design - CPSC332 Programming Language Design - CPSC206 Structured Programming in C/C++* Mentored Undergraduate and Graduate Students

College Station, Tx, Us

* Devised the first published linear time O(n) algorithm to optimally decide on-line if hard real-time firm aperiodic tasks can be guaranteed within periodic hard real-time FP schedules, n = Num of periodic tasks* Devised a constant O(1) time on-line algorithm minimizing completion time of soft real-time aperiodic tasks co-scheduled with HRT periodic ones* Formulated theoretical framework and analytically derived timing properties and limits of extreme periodic task schedules for Hard-Real Time systems for the analysis of scheduling algorithms.* Devised a parallelization of the Steepest-Edge Simplex Algorithm on massively-parallel supercomputers minimizing communication, and achieving 3 orders of magnitude in speed-up.* Designed and Implemented FFT algorithm on Message-Passing Supercomputer and investigated communication and computation scalability vs problem size.* Designed and Implemented a light-weight distributed thread scheduling system where threads are automatically dispatched to compute nodes with lighter load* Performance evaluation of POSIX threads on SMP platforms and investigation of stability and Real-Time readiness* Designed and Implemented ATMSim a discrete-event, discrete-time simulator for full-scale ATM Broadband ISD Networks with flow control and leaky-bucket algorithms under Bernoulli and Bursty types of traffic or actual traffic traces.* Performance evaluation of Multi-Stage Interconnection networks under Bernoulli and Bursty types of traffic (Discrete Event simulation).* Performance evaluation investigation of three alternative Concurrency-Control algorithms for RDBMS and TPMS with Mixtures of Interactive and Batch workloads (Discrete Event simulation)* Designed and Implemented LPBench, a workbench to evaluate the convergence efficiency of five different Pivot-Selection techniques for the Primal and Dual Simplex Linear Programming algorithm

Washington, Dc, Us

* Discrete Event simulator to evaluate time allocation alternatives on Token-Ring networks.* Discrete Event simulator for a parking lot (in ADA)* A Stochastic ContextFree Grammar system for the performance evaluation of different transaction patters on TPMS and DBMS systems.* Design Specification of the File System layer of a modern Operating System.

Doctor Of Philosophy (Ph.D.), Computer Science

Master'S Degree, Computer Science

Bachelor'S Degree, Computer Information Science

Diploma, Elementary School