Co-design study of large scale systems for AI training

Enabling accurate application traffic modeling for future of HPC switches

Developed a library for communication modeling of DL applications for system level simulation and design space exploration for the training systems design

Researched error propagation during quantized network training to obtain numerical boundaries of prediction error increase in quantized networkDeveloped a library for numerical analysis and debugging for compressed network training in PyTorch

Researched ways to accelerate CNN (Convolution Neural Networks) inference using compression techniques Researched CNN architectures with better accuracy-per-computation ratioDeveloped a PyTorch-based library for faster and more accurate compressed CNN training

Researching adaptive routing algorithms and congestion elimination techniques for high-radix networks (pending patent)Proposed new routing algorithm class and congestion detection scheme for exascale-class HPC network router prototypeContributing to development of fast cycle-accurate simulation infrastructure for large scale interconnection networks - SuperSim

Researching adaptive routing algorithms and congestion elimination techniques for high-radix networks (pending patent)Proposed new routing algorithm class and congestion detection scheme for exascale-class HPC network router prototypeContributing to development of fast cycle-accurate simulation infrastructure for large scale interconnection networks - SuperSim

Participation in two large projects: • development of eight-core System-on-Chip with shared L3-cache and directory-based NUMA coherent protocol "Elbrus-4C+" and nominal frequency of 1.3GHz on TSMC 28 nm HPM;• development of dual-core heterogeneous System-on-Chip "Elbrus-2C+" with nominal frequency of 500MHz on TSMC 90 nm.Responsibilities:• Research & Development of micro-architecture specifications on major processor parts• Implementation of RTL models working closely… Show more Participation in two large projects: • development of eight-core System-on-Chip with shared L3-cache and directory-based NUMA coherent protocol "Elbrus-4C+" and nominal frequency of 1.3GHz on TSMC 28 nm HPM;• development of dual-core heterogeneous System-on-Chip "Elbrus-2C+" with nominal frequency of 500MHz on TSMC 90 nm.Responsibilities:• Research & Development of micro-architecture specifications on major processor parts• Implementation of RTL models working closely with validation and implementation teams to meet all functional requirements• Debug, fix and validate pre-silicon issues and bugs using waveform debugging tools and FPGA prototypes • Post-silicon verification of microprocessor’s engineering samples• ASIC design repair using spare gate array repair cells• Supervising students and intern workers including delegating tasks and checking their work Show less

Computer Architecture course lecturer for 5-year studied students