▪ Fifteen years of semiconductor industry experience with a focus on silicon design interaction & co-optimization of cutting-edge, low-power SoCs.▪ Design leader of on-chip adaptive voltage scaling (AVS) sensor suites for Snapdragon chipset. Delivered generations of heterogeneous sensor design (CPR) to GPU/CPU/NPU/DDR high-performance low-power IPs.▪ Expertise in driving gross product margin improvements with embedded solutions. Worked on over 80 SoC designs to achieve cost efficient, performance power co-optimization.▪ Set the methodology with strong post-Si data driven analysis to improve design and silicon correlation. Hands on experience on product yield ramp up and improvement across 20nm, 16nm, 14nm, 11nm, 10nm, 8nm, 7nm, 5nm, 4nm, 3nm technologies.▪ Invented innovative strategies for advanced technology reliability assessment. Enabled de-aging methodology in Qualcomm’s Mobile/AUTO/Compute chipset for reliability mitigation and signoff.▪ Comprehensive knowledge of the circuit design flow, from specification, RTL design to functional verification and physical implementation.▪ Strong collaboration, relationship-building, and communication skills to empower high-performing cross-functional teams to deliver best-in-class power and performance.▪ Over 20 IEEE publications and 7 US patents.
Listed skills include Phone Level Power Management, Battery Charging Design, Phone Thermal Design, Pwb Placement And Routing, and 42 others.