Expertise in digital design including architecture, microarchitecture specification development, integration, RTL coding in Verilog/SystemVerilog, verification. Extensive experience in traceable SoC tape out flows, including synthesis, Lint, LEC, CDC, STA, Tweaker etc. Good knowledge domain on ASIC low-power and low-cost design. Proficiency protocol knowledge: 5G (3GPP), WiFi MAC/PHY (IEEE802.11x)Programming Language: Verilog, System Verilog, VHDL, C, MatlabScript Language: Perl, Python, TCL, MakefileCAD Tools: VCS, NCSim, ModelSim, Verdi, Spyglass, nLint, LEC, PrimeTime, Tweaker, CDC, Git, Perforce