Ming Cai Email & Phone Number

Mountain View, Ca, Us

- CMOS technologist for SoC power-performance KPI improvement of Tensor chips for Google Pixel 8/9 (SF 4LPE/4LPP+) and Pixel 10 (TSMC N3E). - Foundry interface on Silicon data analysis and product correlation to process parametric covering both test chips and SoC products, driving Foundry to technology entitlement- Lead cross-functional efforts across Design/Test/Data teams for technology co-optimization and infrastructure improvement

San Diego, Ca, Us

- Process lead on TSMC 7FF platform responsible for process BSL across wide product portfolio (Modem/SoC/Compute/Auto)- Design/technology co-optimization and product power-performance improvement on SAMSUNG 7nm/5nm for Snapdragon765/765G/768G (7LPP) and Snapdragon888 (5LPE) - Extensive experience interacting with design, product testing and program management to meet customer KPI commitment, sample demand, and product launch schedule

San Diego, Ca, Us

- Process lead on Snapdragon625 (14LPP) managing process optimization, yield bring-up, wafer-level reliability and HTOL qualification - SAMSUNG 14nm/10nm product power-performance improvement and design/technology co-optimization for Snapdragon 820/821 (14LPP), 835 (10LPE) and 845 (10LPP)

San Diego, Ca, Us

- Device owner for TSMC 20SoC technology and process optimization for Snapdragon808/810- Process lead for Snapdragon600 using TSMC 28LP and speed-push process optimization for SnapdragonS4 (MSM8960)- Hand-on experience on statistical analysis for process monitoring, product testing and foundry benchmark

Armonk, New York, Ny, Us

- Device design and technology development on 65-nm and 32-nm HKMG SOI CMOS nodes, including defining and implementing hardware experiments and perform analysis to provide learning for process improvement- Device lead on performance and yield step-up across a variety of elements, including strain engineering, advanced anneals and silicide.- Device owner of a 32-nm testsite with hands-on experiences in chip floorplan, ground rules and design manuals, macro design and layout, test plans and debug- Experience in advanced semiconductor processes, integration flow, manufacturing and fab operations- Close familiarity with device targeting, modeling, simulation and TCAD

Armonk, New York, Ny, Us

- Bench IV/CV characterization of 65-nm SOI CMOS using standard semiconductor parameter analyzer- Proposed a new method to extract body potential of PDSOI MOSFETs resulting an invention disclosure- Developed a new test scheme for negative-bias-temperature-instability study of SRAM FETs

La Jolla, Ca, Us

- Grading homework and project assignments for an advanced graduate-level class (Solid State Electronics)- Running office hours and tutoring for 30+ students with diverse backgrounds

Ph.D., Electrical Engineering

Ms, Solid State Physics