Mitchell Nguyen Email & Phone Number

Santa Clara, CA

Sunnyvale, CA

• Provide Product Engineering leadership to bring complex optical networking products from design to volume production. Own the overall product reliability, manufacturability, testability, and cost-effectiveness..
• Lead Product Engineer for Infinera’s Gen4 Photonic Integrate Circuit (PIC) technology DTN-X platform for long-haul transport market. Including 1.2Tbps Optical Tributary Module OTM-1200, 2 port-100Gbps Tributary.
• Lead Product Engineer for Infinera’s Gen4 PIC technology DTN-X platform for metro-to-regional transport market. Including 400Gbps CFP2-Analog Coherent Optics (ACO) based muxponder line card MXP-400, 400Gbps Optical.
• Lead Product Engineer for Infinera’s Gen3 PIC technology DTN-X platform for long-haul transport market. Including system controller card XCM and all client-optical cards OTM-500, OTM2-500, TIM-1-100GE/G/GX, and.
• Participate and contribute in early design phases from schematic review, lay-out review, mechanical review to functional test and system integration test requirement reviews ensuring products can be reliably built and.
• Well-versed with optical engine ASICs, network protocols framer and mapper ASICs, switch fabric ASICs, embedded processors such PowerPC and FreeScale, Ethernet switches, FPGAs, DRAMs, non-volatile memory devices such.

Sunnyvale, CA

• Responsible for Infinera’s Gen1 & 2 PIC technology DTN platform Common Equipment HWs for long-haul and metro markets - DTC & OTC and MTC chassis. The HWs are PowerPC based system controller cards, high speed.
• Experienced with high-speed digital design up to Gbps speeds.
• Extensive background with control-plane of telecommunication equipment.
• Proficient with OTN, SONET/HDL, Ethernet networking protocols; common interfaces using in telecommunication products such SerDes, PCIe, PCI, MDIO, SPI, I2C, UART, 1-Wire.
• Knowledgeable with Cadence Concept HDL and Allegro (schematic capture and PCB lay-out tools).

Cupertino, CA

• Key member of a hardware team developing carrier class platforms for transport and switching of data, voice, and video traffic. As a lead hardware engineer, designed, debugged, and delivered to production the following.
• Subtended Ring I/O Card. Design included Xilinx Virtex-II FPGAs with 321 Mhz interfaces, CPLDs, SerDes, crosspoint switches, and SFP optical interfaces operating at 3.125Gbps.
• External Search Engine Mezzanine Cards. One design included a Virtex-E FPGA, a CPLD, 2 cascaded CIDR CAMs and a Policy CAM. Another design included 3 cascaded MMC External Search Machine Coprocessors and associated.
• System Controller Card (Syscon). Single-board computer responsible for control all cards in the shelf. Design included PPC750, CPC700, Ethernet controller, Ethernet switches, and various DRAM and SRAM.As a team member.

San Jose, CA

• Member of a team developing all-optical cross-connect switch system based on Semiconductor Optical Amplifiers (SOAs). Accomplishments include:
• 8x8 Optical Crossbar Switch. Designed and debugged of an enhanced version of the switch. Design included: AT Single Board Computer, 8 PLDs to perform decoding function, a set of buffer and latch registers, 72 SOAs and.
• Optical Switch Control Path Module. Designed and debugged of enhanced switch controller. Design included an Intel i960CA processor, SMC LAN9000 Ethernet Controller (10Base-T) family, and CPLD.

Palo Alto, CA

• (Optivision spun off and became ONI Systems, so Optivision and ONI positions effectively represent a continuous term with the same employer).Member of a team developing optical switches and optical network test.
• Optical Switching Node (OSN). Designed, debugged, and released (successfully tested by Sprint’s Advanced Technology Laboratories) an enhanced version of the switch. Design included an Intel i960CA-based processor.
• High Performance Multi-Interface Network Analyzer. Designed and debugged Microprocessor Module. Design included Intel i960-based processor subsystem and 6 PLDs.

Sunnyvale, CA

• Member of New Product Introduction (NPI) Manufacturing team. Worked closely with Hardware Engineering to take new RAID products to production. Successfully released Gladiator, a RAID 5+ fault tolerant, dual-RISC.
• Various design tasks, including performing timing simulation/margin analysis on Altera EPLDs.
• Bring-up of prototype boards, timing measurement/analysis, yield improvement, and failure analysis.
• Provide technical interface between Engineering and Manufacturing, and train production technicians.
• Creating and maintain Viewdraw component symbol library, including responsible for component footprint correctness before release to PCB layout.