Principal Test Engineer, Asics
Current
Apr 2021 - Present
AeroLeads people directory · profile
Michael Kulikowski Email & Phone Number
Principal Test Engineer, ASICs at Marvell Semiconductor
at
Marvell Semiconductor
1 work email found
@marvell.com
4 phones found area 802 and 408
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Current company
Role
Principal Test Engineer, ASICs at Marvell Semiconductor
Location
Essex Junction, Vermont, United States
Who is Michael Kulikowski? Overview
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Quick answer
Michael Kulikowski is listed as Principal Test Engineer, ASICs at Marvell Semiconductor at Marvell Semiconductor, based in Essex Junction, Vermont, United States. AeroLeads shows a work email signal at marvell.com, phone signal with area code 802, 408, and a matched LinkedIn profile for Michael Kulikowski.
Michael Kulikowski previously worked as Principal Test Engineer, ASICs at Marvell Semiconductor and Senior Staff Test Engineer, ASICs at Marvell Semiconductor. Michael Kulikowski holds Bs, Electrical Engineering from University Of Vermont.
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{first}.{last}@marvell.com
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Profile bio
About Michael Kulikowski
Michael Kulikowski is a Principal Test Engineer, ASICs at Marvell Semiconductor at Marvell Semiconductor. He possess expertise in semiconductors, testing, failure analysis, embedded systems, characterization and 32 more skills.
Listed skills include Semiconductors, Testing, Failure Analysis, Embedded Systems, and 33 others.
Current workplace
Michael Kulikowski's current company
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12 roles
Michael Kulikowski work experience
A career timeline built from the work history available for this profile.
Senior Staff Test Engineer, Asics
- Principal Test Development on ASIC 2.5D advanced packaging products. Core focus on interconnect testing, repair, HBM array testing and repair as well as customer integration and development.- Principal Test Development on ASIC Multi-Chip Module products including base ASICs as well as LP/DDR4.- Principal Test Development on partial good test.
Nov 2019 - Apr 2021
Senior Member Of Technical Staff, Td Test Development Engineering
- 20 years industry experience in semiconductor test development, program development as well as quality and 3rd party IP debug.- 2018 GlobalFoundries CEO Award recipient- 2.5D New Product Introduction- Principal Test Development on GF ASIC 2.5D advanced packaging products. Core focus on interconnect testing, repair, HBM array testing and repair as well as.
Mar 2019 - Nov 2019
Member Of Technical Staff, Td Test Development Engineering
- Test development, program development as well as IP debug and fail identification.- IP including HSS (High Speed SerDes), LP/DDR3/4 and HBM (High Bandwidth Memory PHY and stack) core testing.
Apr 2017 - Mar 2019
Member Of Technical Staff, New Technology Qualifications
- Test Team Lead for 14nm T1 qualification, responsible for test/stress schedule as well as priorities of test, stress and data analysis- Product engineer responsible for designs documentation, test specifications, stress conditions and electrical and physical fail characterization for new advanced FinFET process
Jun 2015 - Apr 2017
Technology Development, Semiconductor Research And Development Center
Product engineering for next generation semiconductor technologies including 14nm and beyond.
Dec 2014 - Jun 2015
Embedded Dram Development For Power And System Z Processors
o Primary owner for eDRAM on 22nm system cache memory controller, including test/spec development, yield analysis, failure analysis, system memory subsystem integration and product reliabilityo Responsible for development of array mapping techniques for BIST tested chips to allow detailed array mapping for test, system, field and reliability failso Enabled.
Oct 2012 - Dec 2014
Power And System Z Processor Test Development
o Worked with broad team responsible for eDRAM test development for IBM P and Z series processor caches in 45nm, 32nm and 22nm technologieso Implementation of test methods, system and test characterization, failure analysis, yield and reliability failure analysiso Primary ownership of 32nm technology and product reliability/qualification test programs.
Jul 2008 - Oct 2012
Psram Product And Test Team Leader
o Lead a team of individuals during development, implementation, testing, manufacturing, qualification and customer support of semiconductor memorieso Supported quality topics, internal and external qualifications and ISO requirements, reliability coverage, customer returns and manufacturing capacities and yieldo Supported customer design in activities for.
Sep 2006 - Jun 2008
Back End Known Good Die Product Engineer
o Managed Known Good Die (KGD) qualifications both internally and at customero Highlighted yield improvements, test time reductions and new design for test featureso Managed and oversaw handling of customer returns and closure in shortest amount of time possibleo Provided support to other teams new to the KGD arena providing high level of support and.
Dec 2005 - Aug 2006
Wafer Level Burn-In Product Engineer
o Defined, documented and implemented wafer level burn-in for multiple KGD productso Ensured die level quality equal to server grade component level including many improvements and design for test featureso Maintained position as lead technical contact for wafer level burn-in within the company
Jul 2004 - Nov 2005
Test Equipment Engineer
o Logic applications/equipment engineer on Teradyne J9xx, Advantest 66xx and 67xx, Micro Control Company burn-in with test systems.o Worked to deliver over $300million in equipment/hardware as well as cost savings of $1million to $4million a year, each year.o Test applications engineering including test program improvement and time reduction as well as.
May 2000 - Jul 2004
2 education records
Michael Kulikowski education
Bs, Electrical Engineering
University Of Vermont
As, Electrical Engineering
Vermont Technical College
FAQ
Frequently asked questions about Michael Kulikowski
Quick answers generated from the profile data available on this page.
What company does Michael Kulikowski work for?
Michael Kulikowski works for Marvell Semiconductor.
What is Michael Kulikowski's role at Marvell Semiconductor?
Michael Kulikowski is listed as Principal Test Engineer, ASICs at Marvell Semiconductor at Marvell Semiconductor.
What is Michael Kulikowski's email address?
AeroLeads has found 1 work email signal at @marvell.com for Michael Kulikowski at Marvell Semiconductor.
What is Michael Kulikowski's phone number?
AeroLeads has found 4 phone signal(s) with area code 802, 408 for Michael Kulikowski at Marvell Semiconductor.
Where is Michael Kulikowski based?
Michael Kulikowski is based in Essex Junction, Vermont, United States while working with Marvell Semiconductor.
What companies has Michael Kulikowski worked for?
Michael Kulikowski has worked for Marvell Semiconductor, Globalfoundries, Ibm, and Qimonda Technologies Na.
How can I contact Michael Kulikowski?
You can use AeroLeads to view verified contact signals for Michael Kulikowski at Marvell Semiconductor, including work email, phone, and LinkedIn data when available.
What schools did Michael Kulikowski attend?
Michael Kulikowski holds Bs, Electrical Engineering from University Of Vermont.
What skills is Michael Kulikowski known for?
Michael Kulikowski is listed with skills including Semiconductors, Testing, Failure Analysis, Embedded Systems, Characterization, Debugging, Soc, and Yield.
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