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Mo Yang Email & Phone Number
Senior Staff Digital ASIC Design Engineer
at
Marvell Technology
2 work emails found
@marvell.com
2 phones found area 585
LinkedIn matched
✓ Verified July 2026
4 data sources
Profile completeness 100%
Current company
Role
Senior Staff Digital ASIC Design Engineer
Location
Santa Clara, California, United States
Who is Mo Yang? Overview
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Quick answer
Mo Yang is listed as Senior Staff Digital ASIC Design Engineer at Marvell Technology, based in Santa Clara, California, United States. AeroLeads shows a work email signal at marvell.com, phone signal with area code 585, and a matched LinkedIn profile for Mo Yang.
Mo Yang previously worked as Principal Digital ASIC Design Engineer at Marvell Technology and Staff ASIC Design Engineer at Marvell Technology. Mo Yang holds Master'S Degree, Computer Engineering from Virginia Tech.
Company email context
Email format at Marvell Technology
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{first_initial}{last}@marvell.com
89% confidence
AeroLeads found 2 current-domain work email signals for Mo Yang. Compare company email patterns before reaching out.
Profile bio
About Mo Yang
To work as an ASIC design engineer in an esteemed organization.• ASIC DesignExtensive experiences and knowledge in RTL design, logic synthesis, static timing analysis, power analysis, low-power design• Computer ArchitectureIn-depth knowledge of high-performance CPU/GPU architecture, cache system, interconnection networks• Testing/Veri cationSolid understanding of ATPG, design for testability, built-in-self-test, diagnosis, fault simulation, formal verifi cation• Design ToolsVerilog, SystemVerilog, Synopsys VCS and Design Compiler, Cadence Verilog-XL, NCsim, RTL Compiler and SOC Encounter, DVE, Verdi, Spyglass, PowerArtist, FPGA & Xilinx ISE, Vivado HLS, Modelsim• ProgrammingPython, Unix Shell, Perl, Tcl, C/C++, Java, Multiprocessor Programming• Other skillsStrong teamwork abilities demonstrated in both academic and industry settings.Excellent technical writing and oral presentation skills.
Listed skills include Matlab, Verilog, C++, C, and 26 others.
Current workplace
Mo Yang's current company
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10 roles
Mo Yang work experience
A career timeline built from the work history available for this profile.
Principal Digital Asic Design Engineer
Current
Apr 2024 - Present
Apr 2022 - Mar 2024
Feb 2019 - Mar 2022
Ai Asic Design Engineer
• Designed instruction unit that prefetches instructions from L1 in a ping-pong fashion to cover fetch latency. • Designed load-store unit that performs coalescing to combine load/store requests from multiplethreads in one wave. • Designed scalar buffer which is a large scratchpad memory for acceleration of certain algorithm. Scalar buffer is split into four banks with different access latency based on closeness.
Jul 2018 - Feb 2019
Research Assistant
• Working on implementation attacks and implementation-attack-aware hardware design as a member of Secure Embedded Systems (SES) Lab.
Aug 2016 - May 2018
Teaching Assistant
Teaching Assistant for ECE 4540 VLSI circuit designTeaching Assistant for ECE 4220 Analog IC design
Aug 2016 - May 2018
Research Assistant
• Researching on the project “Reliability and Security Co-design for Nanophotonic Integrated Circuits” and focus on energy-efficient and fault-tolerant nanophotonic network-on-chip design.• Researching on the project “Thermoelectric Nanoengines for Energy Harvesting and On Chip Cooling” and design power conditioning/management circuits for energy harvesting system.• Studying about networks-on-chip especially photonic networks-on-chip in the aspect of topology, switching strategies, routing algorithm, flow control.• Learning about error control coding in VLSI and using Verilog to design architecture for BCH (1023, 1003) code.
Feb 2013 - Jul 2016
Teaching Assistant
Teaching Assistant for ECE 221 Electronic Devices and Circuits 2014 FallTeaching Assistant for ECE 113 Circuits and Signals 2015 Spring
Sep 2014 - May 2015
Lab Assistant
Studied the coupling effects in the multiferroics and research progress in the single phase of Sr3Co2Fe24O41* Prepared and sintered specimens using the solid-state reaction method.* Measured the crystal structure, magnetic properties and magneto-dielectric effect of the specimen using x-ray diffractometer , VSM (Vibrating Sample Magnetometer ) and LCR Meter, respectively.
Sep 2011 - May 2012
3 education records
Mo Yang education
Master'S Degree, Computer Engineering
Virginia Tech
Master'S Degree, Electrical And Computer Engineering, Vlsi, Digital Circuit Design
University Of Rochester
Bachelor'S Degree, Physics
Nanjing University
FAQ
Frequently asked questions about Mo Yang
Quick answers generated from the profile data available on this page.
What company does Mo Yang work for?
Mo Yang works for Marvell Technology.
What is Mo Yang's role at Marvell Technology?
Mo Yang is listed as Senior Staff Digital ASIC Design Engineer at Marvell Technology.
What is Mo Yang's email address?
AeroLeads has found 2 work email signals at @marvell.com for Mo Yang at Marvell Technology.
What is Mo Yang's phone number?
AeroLeads has found 2 phone signal(s) with area code 585 for Mo Yang at Marvell Technology.
Where is Mo Yang based?
Mo Yang is based in Santa Clara, California, United States while working with Marvell Technology.
What companies has Mo Yang worked for?
Mo Yang has worked for Marvell Technology, 天数智芯 Iluvatar, Virginia Tech, University Of Rochester, and Nanjing University.
How can I contact Mo Yang?
You can use AeroLeads to view verified contact signals for Mo Yang at Marvell Technology, including work email, phone, and LinkedIn data when available.
What schools did Mo Yang attend?
Mo Yang holds Master'S Degree, Computer Engineering from Virginia Tech.
What skills is Mo Yang known for?
Mo Yang is listed with skills including Matlab, Verilog, C++, C, Cadence, Fpga, Linux, and Python.
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