Mo Yang

Mo Yang Email and Phone Number

Senior Staff Digital ASIC Design Engineer @ Marvell Technology
Santa Clara, CA, US
Mo Yang's Location
Santa Clara, California, United States, United States
Mo Yang's Contact Details

Mo Yang personal email

n/a

Mo Yang phone numbers

About Mo Yang

To work as an ASIC design engineer in an esteemed organization.• ASIC DesignExtensive experiences and knowledge in RTL design, logic synthesis, static timing analysis, power analysis, low-power design• Computer ArchitectureIn-depth knowledge of high-performance CPU/GPU architecture, cache system, interconnection networks• Testing/Veri cationSolid understanding of ATPG, design for testability, built-in-self-test, diagnosis, fault simulation, formal verifi cation• Design ToolsVerilog, SystemVerilog, Synopsys VCS and Design Compiler, Cadence Verilog-XL, NCsim, RTL Compiler and SOC Encounter, DVE, Verdi, Spyglass, PowerArtist, FPGA & Xilinx ISE, Vivado HLS, Modelsim• ProgrammingPython, Unix Shell, Perl, Tcl, C/C++, Java, Multiprocessor Programming• Other skillsStrong teamwork abilities demonstrated in both academic and industry settings.Excellent technical writing and oral presentation skills.

Mo Yang's Current Company Details
Marvell Technology

Marvell Technology

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Senior Staff Digital ASIC Design Engineer
Santa Clara, CA, US
Mo Yang Work Experience Details
  • Marvell Technology
    Senior Staff Digital Asic Design Engineer
    Marvell Technology
    Santa Clara, Ca, Us
  • Marvell Technology
    Principal Digital Asic Design Engineer
    Marvell Technology Apr 2024 - Present
    Santa Clara, Ca, Us
  • Marvell Technology
    Senior Staff Digital Asic Design Engineer
    Marvell Technology Apr 2022 - Mar 2024
    Santa Clara, Ca, Us
    Working on Serdes Digital Design
  • Marvell Technology
    Staff Asic Design Engineer
    Marvell Technology Feb 2019 - Mar 2022
    Santa Clara, Ca, Us
    Working on Serdes PHY design
  • 天数智芯 Iluvatar
    Ai Asic Design Engineer
    天数智芯 Iluvatar Jul 2018 - Feb 2019
    上海, 上海, Cn
    • Designed instruction unit that prefetches instructions from L1 in a ping-pong fashion to cover fetch latency. • Designed load-store unit that performs coalescing to combine load/store requests from multiplethreads in one wave. • Designed scalar buffer which is a large scratchpad memory for acceleration of certain algorithm. Scalar buffer is split into four banks with different access latency based on closeness.
  • Virginia Tech
    Research Assistant
    Virginia Tech Aug 2016 - May 2018
    Blacksburg, Va, Us
    • Working on implementation attacks and implementation-attack-aware hardware design as a member of Secure Embedded Systems (SES) Lab.
  • Virginia Tech
    Teaching Assistant
    Virginia Tech Aug 2016 - May 2018
    Blacksburg, Va, Us
    Teaching Assistant for ECE 4540 VLSI circuit designTeaching Assistant for ECE 4220 Analog IC design
  • University Of Rochester
    Research Assistant
    University Of Rochester Feb 2013 - Jul 2016
    Rochester, Ny, Us
    • Researching on the project “Reliability and Security Co-design for Nanophotonic Integrated Circuits” and focus on energy-efficient and fault-tolerant nanophotonic network-on-chip design.• Researching on the project “Thermoelectric Nanoengines for Energy Harvesting and On Chip Cooling” and design power conditioning/management circuits for energy harvesting system.• Studying about networks-on-chip especially photonic networks-on-chip in the aspect of topology, switching strategies, routing algorithm, flow control.• Learning about error control coding in VLSI and using Verilog to design architecture for BCH (1023, 1003) code.
  • University Of Rochester
    Teaching Assistant
    University Of Rochester Sep 2014 - May 2015
    Rochester, Ny, Us
    Teaching Assistant for ECE 221 Electronic Devices and Circuits 2014 FallTeaching Assistant for ECE 113 Circuits and Signals 2015 Spring
  • Nanjing University
    Lab Assistant
    Nanjing University Sep 2011 - May 2012
    Nanjing, Jiangsu, Cn
    Studied the coupling effects in the multiferroics and research progress in the single phase of Sr3Co2Fe24O41* Prepared and sintered specimens using the solid-state reaction method.* Measured the crystal structure, magnetic properties and magneto-dielectric effect of the specimen using x-ray diffractometer , VSM (Vibrating Sample Magnetometer ) and LCR Meter, respectively.

Mo Yang Skills

Matlab Verilog C++ C Cadence Fpga Linux Python Analog Circuit Design C Language Eda Rtl Design Circuit Design Embedded Systems Integrated Circuit Design Field Programmable Gate Arrays Computer Architecture Asic Verification Simulations Java Systemverilog Logic Synthesis Static Timing Analysis Low Power Design High Level Synthesis Cadence Tools Synopsys Tools Xinlinx Ise Digital Electronics Pcb Design

Mo Yang Education Details

  • Virginia Tech
    Virginia Tech
    Computer Engineering
  • University Of Rochester
    University Of Rochester
    Digital Circuit Design
  • Nanjing University
    Nanjing University
    Physics

Frequently Asked Questions about Mo Yang

What company does Mo Yang work for?

Mo Yang works for Marvell Technology

What is Mo Yang's role at the current company?

Mo Yang's current role is Senior Staff Digital ASIC Design Engineer.

What is Mo Yang's email address?

Mo Yang's email address is mo****@****ter.edu

What is Mo Yang's direct phone number?

Mo Yang's direct phone number is +158573*****

What schools did Mo Yang attend?

Mo Yang attended Virginia Tech, University Of Rochester, Nanjing University.

What are some of Mo Yang's interests?

Mo Yang has interest in New Technologies, Music, Basketball.

What skills is Mo Yang known for?

Mo Yang has skills like Matlab, Verilog, C++, C, Cadence, Fpga, Linux, Python, Analog Circuit Design, C Language, Eda, Rtl Design.

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