Mohammad R. Fadiheh Email & Phone Number

I am a postdoctoral fellow at Stanford University. My research is focused on advancing the adoption of formal methods for functional and security verification of hardware designs.In the past years, I have been working on Unique Program Execution Checking (UPEC), a novel formal verification technique for detecting vulnerabilities to side-channel attacks in microarchitectural designs. UPEC has been applied to various academic and industrial case studies, has found multiple previously unknown vulnerabilities, and has yielded new insights into the field of hardware security, as covered in the public media (https://www.eetimes.com/side-channel-attacks-on-embedded-processors/).Hardware security transcends into almost all application domains and is relevant to different types of designs. This has given me the chance to work closely on various topics such as computer architecture, hardware design methodologies, and hardware/firmware interactions. Working on a field with immediate industrial applications, I got the opportunity to get hands-on experience with commercial and academic simulation and formal verification tools. I aspire to work towards more widespread adoption of formal methods in digital circuit design, especially for the design of security-critical features of the system. The goal of my future efforts is to democratize formal verification through developing efficient tools and easy-to-use verification methodologies for various system requirements, ranging from safety to security, in order to have reliable and trustworthy electronic systems.