St. Asic Physical Design Engineer
CurrentAs a block owner, I am responsible complete physical design flow (using Synopsys tools) from RTL to GDSII. My role involves collaborating with cross-functional teams, I was responsible for optimizing floorplan to achieve optimal area, power, and performance, and conducting placement and routing to meet timing and congestion requirements and performing static timing analysis (STA) to ensure the design meets timing constraints and debugging and fixing design issues to improve design quality.