I am a highly motivated VLSI Physical Design Engineer with a proven track record of two and a half years in the semiconductor industry. My passion for pushing the boundaries of VLSI design and solving intricate challenges has been the driving force behind my career.Experience Highlights:VLSI Physical Design: In my role, I've gained hands-on experience in various critical aspects of VLSI Physical Design, including:FloorPlanning: I excel in creating strategic floorplans that optimize chip area and performance, ensuring the smooth integration of complex designs.Placement: My expertise in placement techniques enables me to efficiently place standard cells, macros, and custom blocks, meeting stringent design goals and ensuring robust and manufacturable designs.Clock Tree Synthesis: I have a strong background in designing clock distribution networks that minimize skew and power consumption while ensuring robust signal integrity.Routing: I'm adept at routing complex and high-density designs while adhering to strict timing and power constraints. I have successfully resolved the congestion, and routing Issues.ECO Fixes & Power Analysis: I have successfully tackled ECO (Engineering Change Order) challenges, utilizing such as TECO, PECO, MECO, and FECO to resolve timing and power issues, ensuring designs meet their targets. My experience also includes power analysis (EMIR), particularly with tools like RedHawk and Voltus, to optimize power efficiency and ensure reliability.Timing and DRV Debugging: I possess advanced skills in debugging and resolving Timing and DRV issues with the aid of industry-standard tools like Synopsys PrimeTime, Cadence Tempus, and Synopsys Tweaker.Physical and Formal Verification: I have hands-on experience in Physical Verification and Formal Verification, addressing DRC (Design Rule Check), ERC (Electrical Rule Check), LVS (Layout vs. Schematic), and LEC (Logical Equivalence Check) issues across various process nodes, including 3nm, 4nm, 5nm, 6nm, 12nm and 22nm.Education:I hold a Master of Technology in VLSI System Design from CVR College of Engineering, where I gained a solid foundation in semiconductor fundamentals and design principles.I am passionate about contributing to cutting-edge semiconductor technology and thrive in dynamic, collaborative environments. Let's connect and explore how we can drive innovation together in the field of VLSI Physical Design.Feel free to reach out if you're interested in discussing VLSI design, semiconductor challenges, or potential collaboration opportunities.