Mohammad Hasan Email and Phone Number
● Planning, integration, and execution of next generation transistor technology in Intel Pathfinding. ● Comprehensive knowledge about FinFET and Gate-all-around (GAA) transistor architecture, process flow, and device physics. ● End-to-end experience in experiment design and systematic characterization of 7nm technology node at Globalfoundries. ● Design, simulation, and fabrication of biosensors for cancer detection at UTArlington. ● 5+ years of hands-on semiconductor fabrication experience in a class-100 cleanroom in Shimadzu Institute for Research Technology. ● Proactive team player and a fearless leader with strong work ethic. Excellent in project management, presentation, and interpersonal skills ● Inventor of multiple patents
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Process Integration EngineerIntel CorporationPortland, Or, Us -
Staff Integration Engineer: Intel PathfindingIntel Corporation Mar 2018 - PresentHillsboroFront-end process integration engineer at Intel pathfinding team developing the next-generation (beyond FinFET) semiconductor technology. -
Graduate Research AssistantUniversity Of Texas At Arlington Aug 2011 - Dec 2017Shimadzu Institute For Research And TechnologiesWorked in NanoNio Laboratory in Shimadzu Institute for Research and Technologies. My research focus was to design and develop biosensors for POC diagnosis and disease detection. I have successfully completed multiple projects here since Fall 2011. -
Graduate Teaching AssistantUniversity Of Texas At Arlington Aug 2011 - Dec 2017TexasServed as a Graduate Teaching Assistant in Department of Electrical Engineering, UTA from 2011-2016. My job responsibilities included: -Course instructor, Design lab projects for the students-Mentor undergraduate students-Prepare exam paper and assignments, -
InternGlobalfoundries May 2017 - Aug 2017Malta, Ny- Developed infrastructures for automation of systematic failure analysis and effective silicon validation with 7nm hardware data - Analyzed electrical data from DOE process window and process fail-mode test structures to investigate systematic yield detractors - Reviewed test-site macro designs to capture systematic fail-modesPrior experience...- Developed state-of-the-art 7nm CMOS technology by designing test-site macros to identify systematic yield limiters- Conducted Design of Experiment (DOE) to generate electrically testable structures for BEoL Opens/Shorts fail modes - Designed parameterized-cells (pcell) in SKILL for quick and accurate assembly of DOE layouts- Macro verification and Design Rule Check (DRC) to develop ground rule clean macro layouts. -
Research AssistantUniversity Of Texas Arlington Research Institute Jan 2017 - May 20177300 Jack Newell Blvd S, Fort Worth, Tx 76118Explore different nano-bio technologies for cancer diagnosis.
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InternGlobalfoundries May 2016 - Aug 2016East Fishkill- Developed state-of-the-art 7nm CMOS technology by designing testsite macros to identify systematic yield limiters- Conducted Design of Experiment (DOE) to generate electrically testable structures for BEoL Opens/Shorts fail modes - Designed parameterized-cells (pcell) in SKILL for quick and accurate assembly of DOE layouts- Macro verification and Design Rule Check (DRC) to develop ground rule clean macro layouts. -
LecturerUnited International University Feb 2010 - Jul 2011Lecturer in the Department of Electrical and Electronics Engineering.Member of: Center for Energy ResearchCourse Instructed: EEE101: Electrical Circuits-IEEE103: Electrical Circuits-IIEEE220: Electrical Wiring and DraftingEEE305: Power SystemEEE309: Communication TheoryEEE310: Communication System LaboratoryEEE433: Optoelectronics and Optical DevicesEEE456: Digital Communication laboratoryCSI122: Structured Programming Language LaboratoryThesis Supervisor: "Line Following Robot" -
Quantitative Software DeveloperStochastic Logic Limited Oct 2009 - Jul 2011Job Responsibilities:Data mining, Software Development, Algorithm formulation.List Of Projects:1. Support Vector Machine and GA base buy-sell decision making algorithm development.2. "Visualization of fourth dimensional data in two dimensional space". Algorithm development for intelligent clubbing in data‐mining and design of a four‐dimensional Data Analyzer (using MATLAB). 3. Online Computational Module Development for 'Modeling and Pricing of Variance Swaps for Local Stochastic Volatilities with Delay and Jumps'.
Mohammad Hasan Education Details
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Electrical And Electronics Engineering
Frequently Asked Questions about Mohammad Hasan
What company does Mohammad Hasan work for?
Mohammad Hasan works for Intel Corporation
What is Mohammad Hasan's role at the current company?
Mohammad Hasan's current role is Process Integration Engineer.
What schools did Mohammad Hasan attend?
Mohammad Hasan attended The University Of Texas At Arlington, Bangladesh University Of Engineering And Technology.
Who are Mohammad Hasan's colleagues?
Mohammad Hasan's colleagues are Lâm Thị Tiền, Ron Sinicki, Stephen Walling, Nardeen Qassum, John Sissell, Yazan Siam, Sahar Barbalat.
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4unl.edu, gmail.com, unl.edu, unl.edu
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Mohammad Hasan
Piscataway, Nj1unionbank.com -
Mohammad Hasan
Providence, Ri -
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Mohammad Hasan
Morris Plains, Nj
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