High Speed Analog and SERDES design

High Speed Analog, SERDES, and Interface IP design

High Speed Analog and SERDES design.

SERDES (NRZ, PAM4):Duty Cycle Correction circuit for 8-60 GBPS high speed serial link in 14nm CMOS technology. The design involves CML to CMOS converter, high speed buffer, Bias Scheme, Decoder, and Slew Rate control block, comparator.IQ generation and phase interpolator circuit for 8-60 GBPS high speed serial link in 14nm CMOS technology. The design involves poly-phase filters, CML buffers, Mixer, TIA, and active inductor.

Research on intellectual property in the area of wireless and wire-line communication and provide appropriate judgment for the patentability.

SERDES/Re-Timer/Re-driver/High speed Switch (Thunderbolt, Display port, HDMI, SATA, PECL, USB, PCI-e):10+ Gbps FET switches family for Thunderbolt applications. 10.3 Gbps receiver for -18dB return loss, 20mV sensitivity, 26dB input equalization in 65 nm CMOS process for thunderbolt Re-timer. All analog adaptive equalizer for TMDS applications. Driver with slew rate control. EQ that can handle pre-emphasis without causing false transition. Industry’s lowest auto low power (17mW) 3G SATA Re-driver. Link replicator for Fiber channel, Gigabit Ethernet, and HDTV Data rates . 3.3V tolerant HDMI transmitter with slew rate/termination/de-emphasis control for 6Gbps DP to HDMI Translator in 65/90nm CMOS process. Programmable pre-emphasis tolerant multistage equalizer that can compensate up to 18dB loss, for 5.4Gbps display port Re-driver in 90nm CMOS. Receiver, Transmitter, Loss of Signal Detector (LOSD), Customer programmable E-fuse, Battery charging circuit for SERDES product family. Pre-emphasis tolerant programmable EQ for 5 Gbps USB and PCI-e.Re-driver. High speed path for display port to TMDS Translator. CML driver with slew rate control for 2.7Gbps DP to TMDS Translator. Supervised development and simulation effort of Re-driver products. Equalizer for 2.7Gbps Display Port Re-driver . Supervised low power high speed path design for 2.7 Gbps Display Port Re-Driver. 2.7 Gbps equalizer for Display port 1:2 switch with integrated TMDS translator. Mentoring member’s of the high speed interface analog design team and Co-ops on various issues of high speed analog circuit design since 2006. Represented TI in the Display Port (DP 1.3) Standard committee for PHY definition.

1.5 GHz Clock spread spectrum (SSC). HSTL driver, PFD, Charge pump, and VCO for Jitter Cleaner PLL. Crystal oscillator design for remote key less entry (RKE). This oscillator was designed to work with ceramic and crystal resonator. Thermal shutdown circuit design for remote key less entry (RKE) project, design involves temperature sensors, comparators and logics. Power supply with 100dB power supply rejection in 0.25 micron BiCMOS process. This power supply system takes square wave voltage varies from 6.2V to 25 volt from the distributed systems interface (DSI), and generate 5V output with less than mv peak to peak ripple.

868/915 MHz AM/ASK/FM/FSK direct modulation transmitter. Design involves LC Tank VCO, Band-Gap Reference, Pre-scaler, Crystal Oscillator, Phase-Frequency Detector, Charge Pump, Loop Filter, PA Buffer and Driver, and Lock Detect Circuit, High speed dynamic pre-scaler.315/433 MHz AM/ASK direct modulation transmitter. Design involves Voltage Controlled Oscillator, Band-Gap Reference, Pre-scaler, Crystal Oscillator, Phase-Frequency Detector, Charge Pump, Loop Filter, PA Buffer and Driver, and Lock Detect Circuit. 2.4 GHz local oscillator for direct conversion transceiver. The design involves Current mode logic (CML) divider, Mixer, Buffers, variable phase delay and digital logic. Pre-scaler driver amplifier and buffer design for 2.1 GHz Synthesizer.Power efficient transmit VGA for 2.4GHz WLAN transceiver with 1/3 typical die area that provides 25dB gain range.Binary weighted current mode digital to analog converter (DAC) for Transmit IFVGA. Close loop power control Design for WLAN transceiver, design involves Peak detector, Comparator, Analog to Digital converter (ADC), Digital to Analog converter (DAC), and digital logic. 374 MHz Clock generator for I/Q calibration that involves CMOS converter, dynamic logic (TSPC) divider and wide swing low voltage current bias circuit. Low noise voltage regulator for the integrated VCO. Upconverter and PA driver with 28 dB gain control. Input/ Output Driver.TXDATASYNC and Serial port for Bluetooth transceiver.