Design engineer & technical leader with more than 22 years of hands-on experience in high performance CPU/GPU/SoC design across multiple process nodes.Expert in Physical/Structural design implementation (Synthesis, Floorplanning, CTS, PnR, STA) and timing convergence from netlist to GDSII for CPU/GPu/SoC blocks of varied complexities in advanced technologies (>200M gates, 2 GHz+, 15+ tapeout). Skill-sets include but are not limited to power grid, clock tree & low-power reduction implementation, Signal integrity & timing closure methodologies such as OCV/AOCV, Physical Verification, IR drop analysis, Formal verification, Semi-custom GHz+ Clock Tree design, multiple tapeouts in 10nm/14nm/22nm/32nm/45nm/65nm technology, Microarchitecture, RTL/constraint development, Chip-level integration. Vast experience in leadership of defining schedule and managing multiple project milestones, mentoring team of talented engineers and engaging with tool vendors. Expertise in managing design teams including cross-site teams, in driving solutions, formulating operation plans and delivering results. Highly motivated, self-driven and goal-oriented with excellent communication skills