Ethernet MAC Security VerificationDuties: • Developed Verification plan for Ethernet MAC Security module. • Developed configuration files, sequences, tests and updated the Ethernet environment to accommodate MacSeC. • Configured the Ethernet VIP to support MacSeC Ethernet frames. • Developed and integrated checkers and coverage model. • Ran the tests, debugged and filed issues. • Working on coverage closure.The environment used: UVM.CRC Accelerator module - Verification Duties: • Developed Verification plan for CRC Accelerator module. • Developed the environment. Developed base sequence, base test. • Developed and integrated checkers and coverage model. • Ran the tests, debugged and field issues. • Developed stress/directed tests and worked towards coverage closure at SoC level.The environment used: UVM.

Ethernet Subsystem - VerificationDuties: • Developed Verification plan for Ethernet subsystem verification at Subsystem level and SOC level. • Developed the subsystem level environment. Developed configuration, base sequence, base test. • Integrated the Ethernet VIP. • Developed and integrated checkers and coverage model. • Ran bring up tests at subsystem level, debugged and field issues. • Ported the subsystem level env to SoC level env. • Developed tests at SoC level. Ran tests, debugged and field issues. • Updating the environment to accommodate the RTL changes.(Addition of RMII interface) • Worked on stress/directed tests and coverage closure.The environment used: UVM.

5G SoC Verification - DMA based RF_SPI - VerificationDuties: • Developed Verification plan for DMA based RF_SPI module. • Developed mmWave slave UVC and APIS Slave UVC. • Reused top_level SoC env ,added rf_if registers to apb_reg map and connected the slave agents. • Developed test Cases for all scenarios along with corner cases. • Debugged the failures and reported to the design team w.r.t RF_SPI. • Did coverage analysis and worked towards the closure.The environment used: UVM.400 GbE Ethernet Switch - VerificationDuties: • Developed the cluster level testbench in SV/UVM from scratch for the 400G Ethernet project. • Developed Scoreboard, Driver, Monitor and configurable agents from scratch. • Developed verification plan of module environment for 400G Ethernet project. • Developed the module level testbench in SV/UVM from scratch for the 400G Ethernet project. • Debugged the failures and reported to the design team w.r.t bus width converter logic. • Developed test cases for all the scenarios along with specific corner cases. • Did coverage analysis and worked towards the closure. • Developed Driver, monitor and configurable agents from scratch • Coverage closure at module and subsystem levelThe environment used: UVM.

Project: UART Core IP VerificationDuties: • Architected the class-based verification environment in UVM. • Defined Verification Plan. • Verified the RTL module using System Verilog. • Generated functional and code coverage for the RTL verification sign-off.The environment used: UVM.Router 1x3 - Verification Duties: • Architected the block level structure of design and implemented using Verilog HDL. • Verified RTL using System Verilog. • Generated Functional and Code coverage for RTL verification sign-off.The environment used: Systemverilog.