Mohammed Hossain Email and Phone Number
Mohammed Hossain work email
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Mohammed Hossain personal email
Professional Motto:“Committed to continuous improvement in EDA methodologies, delivering sustainable impacts that enhance design workflows and contribute to long-term success in engineering projects.”As an accomplished #EDA/#CADEngineering executive with 35 years of experience, I lead the development of innovative design #AutomationSolutions that streamline complex #Engineering workflows. My expertise spans #HighPerformanceComputing (HPC) systems, #CloudEDA workflows, and advanced #ProcessNodes (3nm to 180nm). I am skilled in #ProgrammingLanguages such as #CadenceSkill, #Perl, #Python, and #C++, and have deep experience with industry-standard EDA tools like #CadenceVirtuoso, #SynopsysDesignCompiler, and #MentorCalibre.I specialize in driving efficiency and performance improvements through #Automation, #Verification, and custom tool #Configurations. I have successfully led cross-functional teams to deliver high-impact solutions that reduce design #CycleTimes and enhance precision. My goal is to continually push the boundaries of EDA technology to enable faster, more efficient design processes and contribute to #OrganizationalSuccess in the #SemiconductorIndustry.With a focus on #StrategicVision and hands-on #TechnicalLeadership, I am dedicated to driving the next generation of EDA solutions that meet the evolving demands of the semiconductor industry. Let’s connect to discuss how we can collaborate and push the boundaries of design automation together!#DesignAutomation #Semiconductor #EngineeringLeadership #Innovation #DesignTools #TechLeadership #CircuitDesign #ElectronicsEngineering #DigitalDesign #TeamCollaboration #EngineeringExcellence #TechnicalStrategy #ProductDevelopment #AgileEngineering #HPC #ContinuousImprovement #EngineeringSolutions
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Director Design Automation EngineeringIntel Corporation Dec 2021 - PresentSanta Clara, California, Us• Lead the development of DRC, LVS, and signal integrity verification methodologies for cutting-edge semiconductor technologies using Calibre and ICV, ensuring high verification accuracy and operational efficiency.• Oversee the administration and enhancement of RF, analog, and digital PDKs, driving improvements in front-end and back-end design processes.• Streamline physical verification efforts, integrating advanced EDA tools and managing cross-functional teams to optimize analog and RF circuit design and verification.• Ensure compliance with industry standards and alignment with organizational goals by effectively managing EDA tool integration and design verification processes.Key Accomplishments: • Architected EDA tools and workflows, including custom scripts and configuration files using Cadence SKILL, Perl, and Python, to streamline design processes and improve tool integration.• Spearheaded developing and validating high-performance custom PCells, integrating them into design libraries, and optimizing simulation and layout in Cadence Virtuoso-XL.• Utilized new tool versions and verification processes, including self-operating solutions for Metal/Polyfill, to support mixed-signal design flows and lower costs. -
Sr. Cad Engineer & ManagerQorvo, Inc. 2018 - 2021Oo• Led integration of EDA tools and version control, optimizing analog/RF design and overseeing comprehensive Tapeout processes to ensure project efficiency.• Oversaw design database management and Tapeout processes, implemented advanced automation, and reduced licensing expenses, streamlining operations and maximizing cost-efficiency.• Engineered custom PDKs and libraries using Cadence Virtuoso-XL with SKILL and Perl scripts, refined CAD methodologies and delivered training to designers to enhance productivity. Key Accomplishments: • Deployed rule decks for various technology nodes, automated EDA tool processes, and developed scripts, improving design accuracy and reliability and minimizing silicon respins, costs, and time. -
Director Cad EngineeringQualcomm 2013 - 2018San Diego, Ca, Us• Supervised the formulation, verification, and maintenance of RF, Analog, and Digital PDKs for Intel’s cutting-edge process nodes and coordinated the integration and support of EDA applications.• Spearheaded the implementation of Pcells and EDA scripts in Cadence Virtuoso-XL, Cadence SKILL, ROD, Perl, and Python, optimizing the design process and advancing tool integration.• Implemented and maintained RF/Analog PDKs across multiple process nodes (14lpprf to 180nm), enhancing design efficiency and eliminating the need for silicon respins through robust validation methods.Key Accomplishments: • Streamlined design processes with new configurations and GUIs and developed CAD automation scripts, achieving cost savings on Assura licenses and boosting operational efficiency. -
Senior Manager Cad EngineeringMicrosemi Jun 2012 - Oct 2013Aliso Viejo, Ca, Us• Oversaw developing and deploying custom and foundry PDKs for various process nodes, ensuring robust design workflows for RF, analog, and mixed-signal circuits.• Led EDA tool setup, configuration, and upkeep, managing integration, physical verification (DRC/LVS/ERC), and Tapeout processes to enhance simulation efficiency and product design outcomes.• Created advanced automation scripts and tools using Cadence SKILL, Perl, Python, and other languages to refine design processes, boost tool performance, and drive cost savings.Key Accomplishments: • Cut time-to-market by leveraging advanced test and validation methods for PDKs, reducing silicon respins, and delivering quality designs across 0.18um/65nm nodes. -
Director Cad EngineeringAmalfi Semiconductor Oct 2005 - Jun 2012Greensboro, Nc, Us• Guided a team of CAD/EDA engineers in advancing analog and mixed-signal designs, concentrating on high-frequency operations and circuit robustness.• Defined design for manufacturability guidelines, constructed parasitic extraction and re-simulation flows, and innovated tools and automation methods to refine design processes.• Coordinated vendor negotiations and cost-saving strategies, including efficient license management and customization, streamlining interactions with foundries such as TSMC and IBM.Key Accomplishments: • Saved costs and elevated design operations by bargaining EDA vendor agreements, maximizing license use, and engineering high-performance custom devices. -
Senior Staff Cad EngineerVolterra Semiconductors 2003 - 2005San Jose, Ca, Us -
Senior Staff Cad EngineerPhilips Semiconductors 1999 - 2003Amsterdam, Noord-Holland, Nl -
Senior Staff Cad EngineerLsi Logic (C-Cube Microsystems) 1998 - 1999San Jose, Ca, Us -
Senior Cad EngineerAnalog Devices May 1995 - Jan 1998Wilmington, Ma, Us -
Lead Consulting EngineerCadence Design Systems 1993 - 1994San Jose, California, Us -
Circuit Design EngineerCirrus Logic 1989 - 1992Austin, Tx, Us
Mohammed Hossain Skills
Mohammed Hossain Education Details
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Utah State UniversityElectrical And Electronics Engineering -
Utah State UniversityElectrical And Electronics Engineering
Frequently Asked Questions about Mohammed Hossain
What company does Mohammed Hossain work for?
Mohammed Hossain works for Intel Corporation
What is Mohammed Hossain's role at the current company?
Mohammed Hossain's current role is Senior Staff Of EDA/CAD Engineering.
What is Mohammed Hossain's email address?
Mohammed Hossain's email address is mo****@****rvo.com
What schools did Mohammed Hossain attend?
Mohammed Hossain attended Utah State University, Utah State University.
What skills is Mohammed Hossain known for?
Mohammed Hossain has skills like Mixed Signal, Analog, Cmos, Semiconductors, Cad, Asic, Ic, Analog Circuit Design, Soc.
Who are Mohammed Hossain's colleagues?
Mohammed Hossain's colleagues are Jeannie Tan, Marie Conte, Cornelia Fetzer, Flemming Erikstrup, Khairul Akmal, Roee Ben-Yishay, Yeh-Chun(Matthew) Lin.
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