Monte Manning Email & Phone Number

Boise, ID

Pathfinding on NAND Fabrication Process Integration, specifically exploring end-of-roadmap issues. Researching revolutionary and disruptive technology to provide options that ensure Micron's continued competitiveness in this market space in the next 5-10 years.

Boise, ID

Took some time away from the Semiconductor Industry pursue other interests and catch up on life.

Boise, ID

Lead effort to implement electro-mechanical carbon nanotube switches onto silicon wafers processed in a conventional fabrication facility. Manage a team located in multiple foundries both domestically and internationally. Development efforts are both in-house and also includes work to implement the CNT memory element in to various wafer diameter and.

Developed revolutionary solutions for end-of roadmap problems. Primarily focused on DRAM though some areas of investigation are generic (eg: isolation, devices, metallization). Developments in FEOL (advanced isolation and 3D devices as well as cost reduction), MOL (low-temperature local interconnect and interlayer pre-metal dielectrics and contacts), DRAM.

Nishiwaki, Hyogo Prefecture, Japan

Japan Production Fab Site Integration into Micron Technology: With local management, review and modify programs and practices to conform to and/or cooperate with Micron Corporate Systems and Standards. Ensure that “best practices” at the local site are not degraded and maintain the high levels of productivity and yields previously proven at the site. Areas.

Boise, ID

16M, 64M, 128M, 256M EDO, Synch, and DDR DRAM Technology Transfer: Responsible for transferring Micron advanced DRAM process technology to newly acquired Micron Family Sites in Italy, Singapore, and Japan. Assist in yield and capacity enhancement at all sites by leveraging world-wide learning and expertise. Control conversions at joint venture sites in.

Boise, ID

64M.21um DRAM Process Integration: Co-managed development and transfer to production.21um and.18um DRAM technology. Responsibilities included: Process specification and integration, wafer processing and dispositioning, split specification and analysis, design rule development, interfacing with design and layout, product engineering during design of 64M.

Boise, ID

2M/4M SRAM Process Integration Manager: Responsible for the team developing a.35um process that cuts the cost of Micron’s.4um process by 50%. Includes all tasks listed above as well as conceptualization of the cell and process to yield ramp into production.. Also involved design and layout of functional 1M SRAM test chip (including DRC, LVS,and Tapeout).

Boise, ID

1M SRAM Process: Reduced incidence of burn-in failures on a mature part due to mobile ionic contamination on an existing production process. Required determination of the source of the contamination for eventual reduction as well as improvement to barriers to ionic drift. Project resulted in over 98% reduction in burn-in failures as well as contributing to.

Assignee from Micron to aid in bringing up the initial processes at Sematech:Phase 1 Process Integration: Integrated AT&T FEOL and IBM BEOL into a single flow. Process used to debug initial installation of Sematech equipment set. Assisted in specifying tracking guidelines and Fab procedures for early Sematech process line.Phase 2 BEOL Process Integration.

Boise, ID

As initial orientation for process integration at Micron, was assigned to production process sustaining of dry etch.

SVHSIC Process Development: Worked to improve VHSIC process to move from R&D to manufacturing. Involved Process and Device simulation (SUPREM, MINIMOS, and PISCES), wafer processing, experimentation and analysis, and test chip design and layout.CMOS Advanced Process Development: Development of future 6T SRAM processes. Experience in process and device.

Individually responsible for the design of a programmable interval timer (82C53). Designed to be pin-to-pin compatible with Intel's 8253. Involved design, SPICE and Logic simulation, layout (custom and std cell), introduction of design into fab, and debug of initial lots.