Founding memberTechnical lead of the Image processing and Hardware development teamSystem architect of the Application Processor based system and Hardware Acceleration with FPGA platform

SOC design lead on a 2G/3G/4G baseband processor with dual ARM and DSP cores, AMBA fabric, 3G/4G DigRF, SDIO/USB, GSM/AES/SHA security/cipher, multiple power domains, 40nm process.SOC design lead on a LTE baseband processor which 4G DigRG interface, AMBA fabric, custom SAR hardware acceleration, AES/Snow3G cipher, multiple power domains. Device fabricated in 65nm.First to market with LTE baseband processor chipset demonstrated at CESDeveloped the deep sleep power management for a 65nm 2G/3G GSM baseband processor with 3G DigRF, ARM9 and DSP cores, OCP fabric.WiMax baseband processor with mixed signal RF interface, ARM9 processor, AES/SHA cipher, OCP fabric, USB/SDIO device interface, multiple power domains. Device fabricated in 65nmDevelopment lead on FPGA based WiMax microcell with Intel IXP network processor, SPI3 interface, PPC stack processor, PLB fabric, and Ethernet backplane. Development system used for Japan field trials for WiMax deploymentFPGA prototyping/SOC verification of baseband processor system in Xilinx/Altera device. Developed proprietary flow for processor register integration and partitioning of the SOC to multiple FPGAs

Design member on an ARM based packet forwarding engine with integrated TCAM lookup for layer 2/3 routing, integrated dual GE MACs.Design lead on the development of a GE traffic manager for the control and data path of a 128 port GE router. Line card support of 4 GE ports with virtual outbound queuing.Design lead on the development of an FPGA based IP/MPLS/ATM fabric and line cards for an edge based router with support for OC48/12/3/GE, SPI4.2 interfaceLead designer on the development of an IP Aware ATM/LANE multi-port OC3/12/48 line card with SPI3 interface.Lead designer on a OC192 SAR/TM with IP/MPLS routing support, interface support for OC12/48/192 POS with a SPI4.1 interface.

Design member on an ARM based packet forwarding engine with integrated TCAM lookup for layer 2/3 routing, integrated dual GE MACs.Design lead on the development of a GE traffic manager for the control and data path of a 128 port GE router. Line card support of 4 GE ports with virtual outbound queuing.

Design of 802.11 DS base band processors with MAC/PLCP hardware acceleration supportDeveloper and lead designer for several PC based chip sets with PCMCIA, PCI, ISA, and 82xx functions

Design of an ASIC used for external DMA and processor interface in a 5 channel GPS receiver.