Successfully developed new unit processes, such as Cu plating and solderable top metal at different foundries (Phoenix Silicon International and NEPES), and resolved process issues, to establish a new technology platform for Power MOSFET at United Microelectronics Corp. (UMC). Define and implement WAT and die sort test conditions and specs. Set up probe card layout and testing conditions for die sort test. Set up design rules and design guidelines with designer and foundry sides. Resolve process and reliability related issues and get the process released.Monitor performance and process stability and prepare for high volume production capability. Interface extensively with external foundry partners and internal R&D engineers, and visited foundries regularly to manage the projects. Assisted in process development for new platform of low cost, 0.35 um Bipolar CMOS DMOS (BCD) technologies at HeJian Technology (HJTC), (an 8” fab in SuZhou, China). This platform is released to mass production.

Cooperated with designers and interfaced with 4 different Asian foundries (8" silicon wafer fab) - Episil, Hua Hong NEC, ASMC and HeJian, to develop and sustain the production lines of power Mosfet.Developed process platform for high voltage products (500V, 600V, 800V and 900V) in HeJian Technology Co. (HJTC) (an 8” fab in SuZhou, China). Transferred and qualified 22 low voltage products of trench power MOSFET (12V to 30V) to Advanced Semiconductor Manufacturing Corporation (ASMC), (an 8” fab in Shanghai, China) in 2 years. All the products meet the performance and quality requirements. Oversee the production line and maintain the yield > 98%.Transferred and developed the high voltage product (500V) in ASMC, and developed super junction (cool MOS) high voltage product. Functional product in 8 months. Developed low voltage products (12V to 100V) in Hua Hong NEC Electronics Co (HHNEC), (an 8” fab in Shanghai, China).Developed process platform for mixed p/n Schottky (MPS) and the trench based process platform of transient voltage suppressor (TVS).Interfaced with Episil (a 5” fab in Taiwan) foundry engineers to sustain the production line of trench power MOSFET and maintained the yield at 93%.

Brought the photo process into control by implement metrology tools and SPC charts to monitor the photo process in the company.The process was done on Indium Phosphide (InP) wafer.

Developed a process for optical wave guide formation on lithium niobate (LiNbO3) wafers and developed a metrology method to monitor and control the process. Worked with other process engineers in starting up a new wafer fab for high volume production for different products.

Sustained etch area of FAB3 production line (a 6" wafer fab, with production of 30,000 wafers per month), and continue developed process for next generation product. Sustained and consolidated the lithography process in FAB3, and improved process capability. Initiated, qualified a CD SEM (Hitachi S-8840) for production line as an automatic CD measurement tool for 0.5um technology. Sustained diffusion and CVD deposition and metal sputtering area.